Research on Sin-Cos Encoder Subdivision Technology

0 Introduction
With the development of automation technology, various sensors are widely used in position detection of servo control systems such as CNC machine tools and robots. Currently, high-resolution photoelectric encoders, resolvers, and sine-cosine encoders are commonly used. Compared with other systems, sine-cosine encoders have unique advantages in improving dynamic characteristics. The sine-cosine encoder outputs the A channel and B channel feedback of the sine-cosine waveform, and calculates the corresponding angle through hardware or software methods. In order to further improve the resolution, electronic subdivision is usually used to increase the repetition frequency of the signal. Electronic subdivision includes software subdivision and hardware subdivision. Software subdivision uses high-speed single-chip microcomputers, DSP, FPGA high-speed digital processing devices, combined with subdivision algorithms. Hardware subdivision includes resistor chain subdivision, space subdivision, and phase-locked frequency multiplication. There are also software and hardware methods used in combination. When using the software subdivision method, the encoder shaft speed fluctuation will affect its subdivision accuracy, and the real-time performance of the system cannot meet the requirements. Based on the above problems, this paper adopts a simple and easy-to-implement hardware subdivision method to increase the resolution of the 512-line sine-cosine encoder to 6 144 p/r, and the conversion rate is fast, the subdivision accuracy is not affected by the fluctuation of the encoder shaft speed, and the cost is low and easy to implement.

1 Subdivision principle
As shown in Figure 1, under ideal conditions, the sine-cosine encoder rotates one cycle and outputs two-phase orthogonal voltage signals (phase A and phase B).

The above A and B phase voltage signals can be expressed as:
UA=Usinθ (1)
UB=Usin(θ+π／2) (2)
Where: U is the output voltage signal amplitude of the sine-cosine encoder; θ is the phase angle of the voltage signal.
The subdivision principle is to select Up corresponding to θp in formula (1) and formula (2) as the voltage reference point for outputting count pulses. When the amplitude of the input signal U≥Up, count pulses are output. When different reference voltages are selected, the encoder rotates a certain angle and outputs a fixed pulse to subdivide the sine-cosine signal.
The design idea is: the encoder sine-cosine signal passes through the voltage comparator. When U≥Up, the voltage comparator outputs 1, and when U [page]

The bias voltage is selected because the actual voltage of the comparator cannot reach 5 V. When the power supply is 9 V, the signal input voltage must also be biased to 4.5 V to obtain a good frequency multiplication result. The circuit simulation is performed using Saber circuit simulation software, and finally the signals Ap and Bp after 12 times the frequency are obtained, as shown in Figures 2 to 4.

2 Circuit logic analysis
In the circuit simulation diagram, the waveform of the comparator output is observed with a logic analyzer. The logic waveform of the comparator in the sine-cosine subdivision circuit is shown in Figure 5 and Figure 6.

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The logical expression of the 12-fold counting pulses [12XA] and [12XB] output after the XOR gate is:

Referring to the comparator waveform diagram and circuit schematic diagram, it can be seen that after the signal passes through the XOR gate, 12 equally divided pulses are output in each cycle, achieving 12 times the frequency, and the frequency multiplication number is consistent with the number of comparators.

3 Result Analysis
After the hardware circuit is built, the oscilloscope is used to display the waveform as shown in Figure 7.

It can be seen from Figure 7 that 12 pulses are output in one cycle, achieving the purpose of subdividing the signal by 12. Compared with the software subdivision method, under dynamic input conditions, the hardware subdivision method effectively improves the subdivision accuracy. The software subdivision method usually requires A/D sampling and angle calculation. Due to the unstable frequency of the input signal, part of the input signal will be lost in the A/D sampling, or the A/D converter will not have time to convert, so that the data cannot be processed in time, affecting the output accuracy of the encoder and limiting the response rate of the encoder. The use of the hardware subdivision method can effectively solve the above problems. Using a comparator to achieve signal multiplication is a good solution at low frequency multiplication. The structure is simple and easy to implement. However, at high frequency multiplication, the number of comparators required to be used increases, and the comparator also has a hysteresis problem, which should be paid attention to in practical applications. Figures 8 to 10 are comparison diagrams of 6x, 10x, and 12x sine and cosine encoders.

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4 Circuit Schematic Diagram
Use 6 LM339 comparators and 5 XOR gates 7486 to build the circuit. The circuit board used for the experiment is shown in Figure 11.

The circuit structure is simple, low cost and easy to implement. From the analysis of the results, it can be seen that with the increase of the frequency multiplication multiple, the hysteresis of the comparator becomes more obvious, so the comparator cannot be used without limit in pursuit of high frequency multiplication.

5 Conclusion
The signal segmentation implemented by this hardware segmentation method has a simple circuit structure, low cost, fast reading, and can meet the requirements of dynamic measurement. Although the hysteresis of the comparator will become more obvious with the increase of the frequency multiplication multiple, it is still a better solution at low frequency multiplication. It is more practical in improving the sine-cosine encoder. This method has been verified to be feasible through simulation debugging and experiments.