Some advice on using new testing techniques and instruments

As semiconductor manufacturers move to 65nm technology and look ahead to smaller nodes, tough test challenges are beginning to emerge. Now, process development engineers must abandon the benign world of silicon, silicon dioxide, polysilicon and aluminum materials and place themselves in the challenging world of silicon germanium (SiGe), silicon on insulator (SOI), hafnium nitrite (HfNO2), metal gate, low-k and copper materials. These new materials impose new test requirements on process and device characteristics. Some of the key applications include advanced high-k gate test, on-wafer RF S-parameter test, isothermal DC and RF test of SOI substrates, and leakage current test down to the quadrillionth ampere (fA) level.

Therefore, traditional DC test methods can no longer provide accurate models for device performance and reliability. Now, correct RF and pulse testing is required throughout the process from modeling to manufacturing, including tests such as determining gate dielectric reliability, high-frequency capacitance values, copper via reliability, and RF performance. Various test methods are changing IV characteristics, RF capacitance-voltage testing, S-parameters, NBTI, TDDB, HCI, SILC, and charge pump (CP).

These new methodologies call for new instrumentation and software that can complete the tests faster. At the same time, the tests must be set up in a way that reduces the time to market and ensures long-term reliability.

The approach that should be adopted

* More on-wafer measurements should be performed to reveal problems in the front-end line (FEOL) process. A key FEOL evaluation task is to establish product reliability related to a specific process, especially for those processes that contain new exotic materials.

* Test equipment and techniques for advanced CMOS technologies should be sought. For example, better methods to characterize via stress migration (VSM) during thermal stress relaxation can be used to obtain good results in 3/4 of the 50-hour isothermal test. This new technology improves failure statistics by cycling temperatures over the maximum propagation rate range and tracking small impedance shifts. Parametric testing at the FEOL may be completed after metal testing, reducing process control feedback time by 50% or more.

* Pulsed DC stress testing should be performed to obtain more diverse data and better understand dynamic phenomena and device performance in frequency-dominated circuits. In particular, short pulse testing can overcome gate leakage and provide an accurate image of interface trap density in charge trap (CT) measurements.

* Test systems with short pulse capabilities and software that include newer test methods should be selected. These systems should be able to provide DC signals and pulse signals with rise times in nanoseconds to a small number of pins without using a switch matrix.

* Choose a parametric test system designed for high-throughput RF testing. They are very different from older systems that were designed primarily for DC IV and CV measurements and then repurposed for RF. New designs can quickly, accurately, and repeatably extract RF parameters with ease of operation that rivals DC testing, and can even perform precise DC and RF testing simultaneously.

Ways to avoid

* Do not limit the testing method to static DC testing. To obtain accurate CT test results, AC and pulsed DC testing are required to qualify the high-k gate dielectric. Dynamic stress measurement techniques such as charge pumps are also valuable in characterizing reliability issues related to NBTI, TDDB, HCI, and SILC.

* Don’t shy away from wafer-level RF parameter testing. Foundry companies are now forced to acknowledge that RF S-parameter measurements are critical in building advanced ICs. As the industry moves to 65nm or finer nodes, extracting the correct RF parameters at frequencies from 1 to 40GHz has become critical for RF compact model verification.

* Don’t rely too heavily on end-of-line reliability testing. Testing packaged devices can be a barrier to uncovering reliability issues and can result in significant cost increases and delays of up to three weeks in shipping time (depending on packaging).

* Don’t stick with the old ways of doing old tests, using old methods, and leveraging old test system designs. For example, the metal material change from aluminum to copper opens the door to new test needs and new test possibilities in areas such as via stress migration and parametric wafer probing prototypes.

* Do not use the same organization and reporting structure for parametric and functional testing, as the economics are very different. Parametric testing uses a sampling strategy for process control and yield improvement, but needs to be evaluated separately. For example, the equipment in a parametric test cell is often widely reused, with up to 85% reuse across 5 or more process nodes.

Figure 1: Static DC measurements are no longer sufficient for high-k dielectrics, and AC and pulsed DC testing are required to characterize charge trapping effects.

1. Perform "detrap" before the signal rises to clear the interface charge

2. Up-trace capture

3. Charge trapping in the transistor on-state

4. Down-trace capture

5. Source: Keithley Instruments, Inc.