Electromagnetic compatibility testing of integrated circuits

The electromagnetic compatibility of integrated circuits is becoming more and more important. Electronic equipment and system suppliers strive to improve their products to meet electromagnetic compatibility specifications, reduce electromagnetic emissions and enhance anti-interference capabilities. In the past, integrated circuit suppliers only cared about cost, application areas and performance, and rarely considered electromagnetic compatibility issues. Even though a single integrated circuit usually does not generate large radiation, it often becomes the source of radiation emissions from electronic systems. When a large number of digital signals are switched at the same time, many high-frequency components are generated.

Especially in recent years, the frequency of integrated circuits has become higher and higher, the number of integrated transistors has increased, the power supply voltage of integrated circuits has become lower and lower, and the chip feature size has been further reduced, but more and more functions, even a complete system, can be integrated into a single chip. These developments have made chip-level electromagnetic compatibility more prominent. Now, integrated circuit suppliers must also consider the electromagnetic compatibility of their products.

Standardization of Electromagnetic Compatibility of Integrated Circuits

Since the electromagnetic compatibility of integrated circuits is a relatively new discipline, although there are relatively detailed electromagnetic compatibility standards for electronic equipment and subsystems, the testing standards for integrated circuits are relatively backward. The 47A Technical Subcommittee of the International Electrotechnical Commission (IEC SC47A) started research on electromagnetic compatibility standards for integrated circuits as early as 1990. In addition, the Society of Automotive Engineers in North America has also begun to formulate its own electromagnetic compatibility test standard for integrated circuits, SAE J 1752, which mainly focuses on the emission test part. In 1997, the ninth working group WG9 of IEC SC47A was established to specialize in the electromagnetic compatibility test methods for integrated circuits. With reference to the suggestions of various countries, it has successively published the 150kHz~1GHz integrated circuit electromagnetic emission test standard IEC61967 and the integrated circuit electromagnetic immunity standard IEC62132. In addition, in terms of pulse immunity, WG9 is also formulating the relevant standard IEC62215.

Currently, the IEC61967 standard is used for electromagnetic emission testing of integrated circuits with a frequency of 150kHz~1GHz, including the following six parts:

The IEC62132 standard is used for electromagnetic immunity testing of integrated circuits with a frequency of 150kHz~1GHz, and includes the following five parts:

The IEC62215 standard is used for pulse immunity testing of integrated circuits and includes the following three parts, but has not yet been officially published:

Electromagnetic emission test standard IEC61967

General Terms and Definitions

The general conditions and definitions of IEC61967 include the following:

Sensors: TEM chamber, field probe, etc.

Spectrum analyzer or receiver: The frequency range covers 150kHz-1GHz, with peak detection and maximum value hold function. The resolution bandwidth settings are as follows:

Table 1: Resolution bandwidth selection.

Power supply: battery powered or a power supply with low RF noise;

Test temperature: 23℃±5 ℃ ;

Environmental noise: When the power supply is supplied to the peripheral circuits other than the IC under test, the measured background noise is at least 6dB lower than the limit. If necessary, a preamplifier can be used.

Test circuit board: Usually, integrated circuit testing needs to be installed on a printed circuit board. In order to improve the convenience and repeatability of the test, the standard stipulates the specifications of the circuit board. As shown in the figure below, the size of the standard circuit board matches the size of the opening at the top of the TEM chamber. The board can integrate the 1Ω/150Ω direct coupling method impedance matching network required for IEC61967 emission testing, the traces for the magnetic field probe method test, and the coupling capacitors used in IEC62132-4.

Figure 1: Standard integrated circuit test board.

TEM chamber method

Figure 2: Schematic diagram of TEM chamber method radiation emission test.

The TEM cell is actually a modified coaxial line: in the middle of this coaxial line, a flat core board serves as the inner conductor, the outer conductor is square, and the two ends are tapered to transition to the universal coaxial assembly. One end is connected to the coaxial line to the test receiver, and the other end is connected to the matching load, as shown in the figure below. There is a square opening at the top of the outer conductor of the cell for installing the test circuit board. Among them, one side of the integrated circuit is installed on the inside of the cell, and the side of the interconnection machine and the peripheral circuit faces outward. In this way, the measured radiation emission mainly comes from the IC chip under test. The high-frequency current generated by the chip under test flows on the interconnection wires, and those welding pins and packaging connections act as radiation emission antennas. When the test frequency is lower than the first-order high-order mode frequency of the TEM cell, only the main mode TEM mode is transmitted. At this time, the test voltage at the TEM cell port has a good quantitative relationship with the emission size of the interference source. Therefore, this voltage value can be used to evaluate the radiation emission size of the integrated circuit chip.

Surface scanning method

Figure 3: Surface scanning test diagram.

This part of the IEC 61967 standard can test the spatial distribution of the electric and magnetic fields on the surface of the integrated circuit. The test diagram is as follows: Use an electric field probe or a magnetic field probe to mechanically scan the surface of the integrated circuit, record the frequency, emission value and spatial position of the probe each time, and post-process through software. The spatial distribution diagram of the field strength at each frequency point can be represented by a colored spectrum. The effect that this method can achieve is closely related to the accuracy of the mechanical positioning system and the size of the probe used. This method can be used for general PCBs, so it is not necessary to use the standard test circuit board recommended in IEC61967-1. By scanning the electric and magnetic fields on the surface of the integrated circuit, the area with excessive electromagnetic radiation in the integrated circuit package can be accurately located. The standard recommends the use of partially shielded micro electric field probes and single-turn micro magnetic field probes. Both of these near-field probes can be made with 0.5mm semi-rigid coaxial cables.

1Ω/150Ω direct coupling method

Figure 4: 1Ω/150Ω direct coupling method test diagram

IEC61967-4 is divided into two methods: 1Ω test method and 150Ω test method. The 1Ω test method is used to test the total interference current on the ground pin, and the 150Ω test method is used to test the interference voltage of the output port. The RF current leaving the chip converges to the ground pin of the integrated circuit, so the measurement of the RF current in the ground loop can better reflect the electromagnetic interference of the integrated circuit. Using a 1Ω resistor in series in the ground loop can be used to obtain the RF current of the ground loop on the one hand; on the other hand, it can achieve impedance matching between the test equipment and the ground pin end. The 150Ω test method can be used to test the interference voltage of a single or multiple output signal lines. The 150Ω impedance represents the statistical average of the common mode impedance of the harness. In order to achieve the matching of the 150Ω common mode impedance with the 50Ω test system impedance, an impedance matching network must be used. The test diagram is shown below.

Faraday cage method (WFC)

Figure 5: Schematic diagram of Faraday cage emission test.

The Faraday cage method can test the conducted interference voltage of power lines and input and output signal lines. Put the standard circuit board or application circuit board with integrated circuits into the Faraday cage. The power lines and signal lines must be filtered when entering and leaving the Faraday cage. The test port on the Faraday cage is connected to the test instrument, and the port to be tested is connected to a 50Ω matching load. The better shielding environment reduces the background noise of the test. The test path is connected in series with a 100Ω resistor to achieve the matching of 150Ω common mode impedance and 50Ω RF impedance. The test schematic diagram is shown below.

Magnetic field probe method

Figure 6: Schematic diagram of magnetic field probe method test.

The magnetic field probe method is to evaluate the electromagnetic emission of integrated circuits by testing the current on the PCB board conductor. The chip pins are connected to the power supply or peripheral circuit through the conductors on the PCB board . The RF current it generates can be obtained by a nearby magnetic field probe. According to the law of electromagnetic induction, the voltage at the output end of the probe is proportional to the RF current on the conductor. The structural details and recommended dimensions of the magnetic field probe are described in detail in the standard. The test diagram is shown below:

Electromagnetic immunity test method IEC62132

General Terms and Definitions

In order to evaluate the chip's immunity performance, an easy-to-implement and repeatable test method is needed. The chip's immunity can be divided into radiated immunity and conducted immunity, and the RF power when the integrated circuit fails needs to be obtained. The immunity test divides the performance status of the integrated circuit into five levels. During the test, continuous wave and amplitude modulated wave tests are performed separately, and the modulation method also uses 1kHz 80% modulation depth peak level constant amplitude modulation. These requirements are similar to the immunity test standard ISO11452 for automotive parts.

TEM chamber method

Figure 7: TEM chamber method radiation immunity test schematic

The TEM chamber in IEC61967-2 can also be used for immunity testing. The receiver at one end of the chamber is replaced with a signal source and a power amplifier, and the other end of the chamber is connected to an appropriate matching load. The TEM wave established in the chamber is very similar to the far-field TEM wave, which is suitable for electromagnetic immunity testing. In addition, in order to monitor the working status of the integrated circuit in real time, supporting status monitoring equipment is also required. The test diagram is as follows:

Bulk Current Injection (BCI)

Figure 8: Schematic diagram of BCI testing.

This method injects interference power into a single cable or harness connected to the pin of an integrated circuit. The cable under test generates interference current due to inductive coupling through the injection probe. The magnitude of this current can be measured by another current probe. This method is actually developed from the automotive electronics immunity test, which can be found in ISO11452-4. The test diagram is shown below:

Direct RF Power Injection (DPI)

Figure 9: DPI test diagram.

In contrast to the inductive injection method used in the BCI method, the capacitive injection method is used in the DPI method. The RF signal is directly injected into a single pin or a group of pins on the chip. The coupling capacitor also has an isolation function, which prevents the DC voltage from being directly applied to the output of the power amplifier. The test diagram is shown below:

Faraday cage method WFC

Figure 10: Schematic diagram of Faraday cage method immunity test.

The Faraday cage conducted immunity measurement method uses the Faraday cage of IEC61967-5. You only need to replace the receiver with a signal source and a power amplifier. The test diagram is shown below. The shielding structure and good filtering limit the RF interference signal to the inside of the Faraday cage, which can effectively protect the test operators.

Test System Solution Example

Figure 11: Configuration diagram for integrated circuit electromagnetic emission testing.

Figure 12: Integrated circuit electromagnetic immunity test configuration diagram.

In response to the various tests of IEC61967, R&S has proposed the certified receiver R&S ESCI, which can complete the integrated circuit electromagnetic emission test standard in combination with various accessories. R&S ESCI has the functions of both receiver and spectrum analyzer, and fully complies with the standard CISPR16-1-1. The operating frequency range is 9kHz~3GHz, with built-in preselector and 20dB preamplifier, peak, quasi-peak, effective value, linear average and CISPR average detectors. Each detector can be displayed in a bar graph and has a peak hold function. It can be remotely controlled by the R&S EMC32 software package through the GPIB bus interface. The emission test configuration is shown in the figure below.

For various immunity tests of IEC62132, R&S uses the integrated test system R&S IMS, combined with various accessories, to complete all IC immunity tests. R&S IMS is a compact test equipment, covering the frequency of 9kHz~3GHz, with built-in signal source, switch, power meter and power amplifier, and can also control external power amplifier; remote control can be achieved by R&S EMC32 software package through GPIB bus interface, and the immunity test configuration is shown in the figure below.

With the continuous growth of operating frequency and chip complexity, integrated circuit electromagnetic radiation and immunity testing must also continue to develop to adapt to new requirements: the test is developing towards high frequency. In order to break the 1GHz limit, many countries and companies have adopted the GTEM chamber method to make up for the insufficient frequency limit of TEM chamber test; the standardization of pulse immunity testing is also in progress. The upcoming standard IEC62215 will complement IEC62132 and is expected to more comprehensively consider the situation when integrated circuits are subjected to electromagnetic interference.