Measuring interconnect impedance of disk drive flex circuits

The link that requires careful design in the HDD is the interconnect between the preamplifier and the read/write head assembly. This interconnect is a key component that enables the HDD to read and write large amounts of data at multiple Gb/s rates, but effects such as intermodulation distortion, overshoot, and undershoot often degrade the performance of the interconnect. This article briefly describes how to measure the impedance of this interconnect using time domain reflectometry instruments.

The link that requires careful design in an HDD is the interconnect between the preamplifier and the read/write head assembly. This interconnect is a critical component to ensure the speed and control required for HDDs to read and write large amounts of data at multiple Gb/s rates, but effects such as intermodulation distortion, overshoot, and undershoot often degrade the performance of the interconnect and significantly delay the design process, even affecting product performance or delaying time to market.

Faced with this challenge, engineers at 3M Asia Pacific are integrating electronic design automation (EDA) technology into the entire design cycle to ensure that HDD flexible interconnects meet development time and cost targets while ensuring their advanced performance. The results they obtained through simulation have been verified using time domain reflectometry (TDR) instruments.

Design Challenges

The motivation for using EDA tools in the design of this article is to shorten the time required to design a product and bring it to market, and to achieve a more robust design. Robustness is achieved by allowing the entire set of design-layout-analysis-debug operations to be performed more frequently and faster, and the cost is significantly reduced compared to manufacturing and measuring prototypes.

3M Microflex circuits are thin, lightweight signal traces placed on a substrate with precisely engineered circuit features. They are used in IC packaging, HDDs, medical devices, printers, and other high-density applications. Flexible circuit technology makes products smaller, lighter, and faster, and can reduce overall application costs.

The circuit to be measured in this article is a flexible suspension structure (FOS) used in a HDD gimbal assembly head (HGA). The design guidelines include three aspects: mechanical compatibility, process independence, and electrical performance.

1. HGA mechanical compatibility: In the gimbal assembly area, the strength of the HGA must be minimized to ensure the flying height compatibility of the head and the recording medium, which requires reducing the conductor height of the circuit, thus affecting the impedance of the entire circuit.

2. Processing independence: 3M's current processing capability is 25 micron line width and line spacing.

3. Electrical performance: The entire flexible circuit requires controlled impedance from the driver chip output to the giant magnetoresistive read/write head.

FOS Design and Analysis

The extraction of impedance (R), inductance (L), capacitance (C), and conductance (G) is done using Spicelink, an electromagnetic field solver from Ansoft. The stackup of different layers of the FOS (Figure 1) assembly is built within the built-in 2D modeling tool. Each layer of the stackup is assigned different material properties, including line width, substrate, adhesive, steel structure support, etc.

Spicelink’s variable parameter capabilities enable engineers to study the effects of variations in line spacing and stacking combinations, thereby evaluating the impact of various changes on circuit performance based on “what-if” assumptions. Figure 2 shows a series of simulation views. Figure 2 shows a cross-section of this stacking combination on the upper left, Figure 2 shows the RLCG matrix calculated using the 2D extractor on the lower left, and Figure 2 shows the electromagnetic field diagrams generated by the simulator on the upper right and lower right. The results of the parametric study in Figure 3 show the effects of line width and line spacing on the impedance of the FOS flexible circuit.

Extracting impedance characteristics through TDR

TDR can be used to measure the impedance characteristics of flexible structures. Virtual TDR is achieved by performing a series of operations to extract the model from the EM simulation and then performing a time domain simulation using a SPICE circuit simulator. The simulation results are highly consistent with the experimental results measured from the TDR instrument.

Figure 4 illustrates the principle of TDR measurement. The impedance characteristics of the circuit are plotted from the reflection waveform. The TDR results show that the impedance along most of the signal transmission path is controlled to 75-80 ohms (Figure 5). This will ensure that the reflections caused by the impedance mismatch of the circuit are suppressed to a small enough range to ensure the target impedance for the normal operation of the circuit. If the reflection cannot be reduced, then the attenuation and distortion will make the signal that finally reaches the preamplifier end unusable.

Intermodulation Analysis

Of particular concern in FOS assembly is the crosstalk between the write and read channels in the circuit. For a 50 ohm circuit, the typical read cycle current is a factorial of 5 mA, which means that in order for the HGA read/write head to not be damaged, the read channel must withstand a maximum voltage of 250 mV.

To analyze this situation, the SPICE model is extracted from the 3D EM simulation tool, focusing on the critical areas of the FOS assembly structure (Figure 6). The HGA area and the tail of the circuit are shown in Figure 6. After the circuit model is extracted, a time domain simulation is performed to determine the intermodulation level.

Figure 7 shows the output waveform generated by the circuit simulation. As shown in Figure 8, the intermodulation voltage level of the FOS structure falls within the maximum limit. These intermodulation diagrams help keep the size of the FOS as small as possible and the packaging as dense as possible while maintaining adequate performance to avoid damaging the head.

Conclusion

The performance of the flex circuit can be determined by performing parametric extraction of the circuit. These analyses include characteristic impedance simulation of the transmission line before layout and intermodulation, overshoot, and undershoot analysis after layout. The impedance characteristics of the entire structure can be obtained by performing virtual TDR. In addition, impedance variations along the transmission line and stack-up are measured.

The typical FOS prototype manufacturing and testing cycle includes manufacturing and assembling flexible circuits on HGA, which takes 5 to 6 weeks to complete. Using Ansoft's Spicelink technology in the design process can effectively reduce the time to 4-5 days. In addition, without increasing the time and cost associated with manufacturing and testing, the use of EDA tools can obtain a more robust design by quickly performing tolerance analysis.

Predicting the performance of new designs before production ensures that unwanted electrical effects can be identified and corrected. Introducing Ansoft's EDA tools into 3M's flexible design process has significantly reduced costs and shortened time to market.

References:

1. Howard W. Johnson, Martin Graham. "High Speed ​​Digital Design: A Handbook of Black Magic." Prentice Hall PTR, 1993.

2. Robert Dodsworth, George Hare. "HGA Technology Driver-The Need for Speed." CleanRooms/DataStor Asia, 2001.

3. Eric Jensen, Mike Resso, Dima Smolyansky, Laurie Taira-Griffin. "Improved Method for Characterizing and Modeling Gigabit Flex-Circuit Based Interconnects." DesignCon, 2001.