SAR antenna platform test module based on PXI bus

PXI Bus Technology Introduction

PXI bus technology is a new open, modular instrument bus specification released by NI, which is an extension of PCI bus in the instrument field. It develops PCI bus technology defined by CompactPCI specification into mechanical, electrical and software specifications suitable for test, measurement and data acquisition applications. PXI bus has exactly the same performance as desktop PCI specification, and is formed by adding mature technical specifications and requirements to PCI bus core technology. It meets the requirements of test and measurement users by adding trigger bus and reference clock for multi-board synchronization, star trigger bus for precise timing, and local bus for high-speed communication between adjacent modules. PXI specification adds environmental testing and active cooling requirements to CompactPCI mechanical specification to ensure interoperability of multi-vendor products and easy integration of systems. It defines Microsoft Windows NT and Windows 95 as its standard software framework, and requires that all instrument modules must have Win32 device drivers written according to VISA specification, making PXI a system-level specification, ensuring easy integration and use of the system, thereby further reducing the development costs of end users.

Structure of the test module

As a PXI bus test card based on the Windows platform, the instrument module includes two parts: the PXI card and the host driver software. The PXI card is responsible for the processing of test data, and the host driver is responsible for communication.

Structure of the PXI card

The PXI card is functionally divided into three parts: the incremental encoder decoding module, the RS-232 interface module, the DSP main processor, and the PXI bus interface. The structure of the test card is shown in Figure 1. The incremental encoder decoding module cooperates with the 422 differential receiver to decode the two-axis position data of the antenna simulation turntable; the DSP main processor completes the processing of the test data, and the PXI interface module mainly completes the conversion interface from the PCI bus signal to the local bus; the RS-232 interface module accepts the serial output signal of the PSD (photosensitive position detector), and the PSD is used in the test system to detect the tracking error of the antenna platform and the simulation turntable movement.



Figure 1 Structure of PXI card

Reading of PSD serial output signal

The test system uses PSD processing circuit to send a frame of data every 5ms through the standard asynchronous serial port. TI TMS320VC5510 is used as the main processor to meet the requirements of data storage space (up to 176KB RAM inside), but it only has McBSP for synchronous communication and cannot directly implement asynchronous serial communication. It needs to cooperate with DSP's DMA channel to realize asynchronous communication through software. Each byte sent by PSD is regarded as a frame of data, and the falling edge of the start bit is used as the frame synchronization signal. The oversampling method is adopted to treat each bit (including the start bit) as a 16-bit word, and the stop bit only samples 8-bit word. A byte is buffered to a fixed buffer through the DMA channel. When a frame of data (10 words) is fully sampled, a DMA interrupt is sent to notify the DSP to process. For the common phenomenon of startup misalignment and garbled characters in serial communication, the special bits are judged and discarded.

Design of incremental encoder decoding module

This test module needs to receive the position information of the platform from the antenna platform test simulation turntable. In various motion control systems, incremental photoelectric encoders are often used as feedback detection elements. Its output is A and B two-phase signals with a phase difference of 90 degrees and a periodic pulse reset signal Z. The positive and negative difference between the A and B two-phase signals determines the positive and negative directions of the movement. The pulse output count of the A and B two-phase signals determines the size of the position movement. Z is a zero-crossing reset pulse. The entire decoding logic design is shown in Figure 2. Since the position information of the simulation turntable used in this test system has two directions, azimuth and roll, two sets of decoders are required to decode the position information in the two directions respectively. Figure 2 Decoding logic design



The

workflow of the main processor

DSP is the key component of the test card, responsible for data processing, storage, simulation of inertial navigation data generation, and communication with the host computer. DSP uses the data sent by PSD as the time reference. After receiving and storing the data sent by PSD every 5ms, it first reads the count value of the counter from the incremental encoder decoding module through EMIF (Extern Memory Interface), converts it into two 16-bit angle quantities through proportional operation, stores it and sends it to the external inertial navigation data simulation module through the EMIF interface, converts it into the self-synchronous angle machine signal output by the inertial navigation and sends it to the stable platform. In order to ensure continuous data recording, the data is stored in the DSP's DARAM (Dual-Access RAM) and uses ping-pong storage (that is, there are two storage areas. When one of the storage areas is full, an interrupt is sent to the upper computer through the PXI bus, and then data is written to the other storage area). We set each storage area to store 1000 groups of data (each group includes 4 data of the electric control turntable azimuth, roll attitude and platform tracking error in these two directions), so each storage area includes 4000 words.

PXI bus interface hardware design

This test card uses the 16-bit EHPI (Enhanced Host-Port Interface) of DSP to connect to the Local bus of PCI 9030 chip. EHPI can read the internal DARAM, internal SARAM (Single-Access RAM) and part of the external storage space of CE0 chip selection through DMA controller without interfering with the normal operation of DSP system, up to 1MB. In this way, the upper computer can obtain the required test data in the internal storage area of ​​DSP through PXI bus without affecting the normal operation of DSP.

PXI bus interface driver

This test module works in Windows 2000 operating system, and the corresponding WDM driver needs to be developed. The driver mainly completes three functions: access to PCI 9030 configuration space, access to DSP memory space and interrupt processing, and communication between application and driver. DSP uses two storage areas for ping-pong storage. When the data in one storage area is ready, an interrupt is sent to the computer through PXI bus. The driver handles the interrupt and reads the data in the storage area of ​​DSP.

Considering the use of object-oriented driver framework to simplify the driver development process, DriverWorks based on Windows DDK as the underlying support is selected as the driver development platform. The DriverWizard wizard tool can establish the driver framework in the VC environment. Here we mainly introduce several functional modules in the driver.

(1) Access 9030 configuration space. When generating the driver framework, the required memory mapping resources have been declared for the configuration registers of 9030, and a KMemoryRange class instance m_MemoryRange is generated. This class obtains the address range of the 9030 hardware register configuration space when the driver is initialized, so that the inb and outb of this instance can be used to implement the read and write operations of the hardware registers respectively.

(2) Access DSP memory space and interrupt processing, that is, read and write operations on the DSP storage area. When generating the driver framework, the required memory mapping resources have been declared for the local bus space of 9030, and a KMemoryRange class instance m_LocalAddSpace0 has been generated. This class obtains the system address range of the local bus geological space of 9030 when the driver is initialized; at the same time, the driver also generates an instance of the KDeferredCall class m_DpcFor_Irq, which is used to call the interrupt delay handler DpcFor_Irq(). When the test card generates an interrupt, the driver captures the interrupt, performs corresponding processing, and then calls DpcFor_Irq() through m_DpcFor_Irq. In DpcFor_Irq(), read and write operations are performed on the DSP storage area through inb and outb of m_LocalAddSpace0. The read data is stored in the system buffer requested in advance (only read operations are involved here).

(3) Communication between the application and the driver. First, the application calls the driver's read and write routine Read() through the API function provided by the operating system (only read operations are involved here). The Read() routine calls StartIo() to queue the read request to avoid conflicts between read and write operations. StartIo() calls the SerialRead() routine to perform specific read operations, that is, to transfer the data in the previously requested system buffer to the user buffer to complete the required read operation.