Radar video accumulation circuit based on charge coupled device

O Introduction
The signal accumulation of early pulse radars mainly relies on the afterglow characteristics of the display and the storage capacity of the radar operator's eyes and brain. Since this accumulation involves many human factors, strict requirements are also put forward for the afterglow performance of the display, and the accumulation effect varies from person to person. Therefore, in recent years, with the development of large-scale integrated circuits and high-speed microprocessors, people have proposed many feasible technical solutions to transform old radars and give full play to the performance of old radars. Radar signal accumulation can effectively improve the radar's signal-to-noise ratio, improve the radar's detection capability, and achieve the purpose of increasing the radar's detection probability and detection distance. Radar signal accumulation is divided into coherent accumulation and incoherent accumulation. Coherent accumulation means that the radar's transmit and receive carrier frequencies have a certain phase relationship, and the accumulation is realized in the intermediate frequency. Incoherent accumulation means that the radar's transmit and receive carrier frequencies have no certain phase relationship, and the accumulation is realized after detection. Most of the early radars are incoherent radars. Therefore, the signal accumulation of this type of radar should be after detection, which belongs to video accumulation. Video accumulation is simpler and easier than intermediate frequency accumulation. In terms of means, it can be realized by microprocessor and software programming, or by charge-coupled devices and their circuits. The video accumulation circuit implemented with charge coupled devices introduced in this article is low-cost and suitable for use in medium and high-end radars or for the transformation of old radars.

The noise power is increased by N times. Then the signal-to-noise ratio of the output voltage after accumulation is Therefore, the voltage signal-to-noise ratio is improved as follows: the signal-to-noise power ratio is increased by N times.

2 Design Scheme
To realize the accumulation and addition of radar signals, a simple scheme is to delay the radar echo signal by one radar transmission pulse cycle, and add it to the echo signal without delay in sequence to achieve signal accumulation. This scheme adopts a recursive video accumulation circuit, the principle of which is shown in Figure 1. Since the delay line is a linear network, the output y(t) through the linear network is the convolution of the input x(t) and the network impulse response h(t).

(βl is the feedback network gain, which should be less than 1)
From the transfer function, we can see that the accumulator is a single-pole system, which has a pole at β1 in the Z plane, as shown in Figure 2. Since Z=esTr, substituting S=jω into the transfer function yields the frequency characteristics of the accumulator;

|H1(ω)| is the maximum value: When ωTr=(2n+1)π, |H1(ω)| is the minimum. The frequency characteristics are shown in Figure 3. Therefore, the accumulator is actually a linear comb filter.

3 Performance introduction of CCD321 type charge coupled device
The charge coupled device CCD321 is an electrically variable analog delay line that can complete the delay of electrical signals and temporary storage of analog information, time correlation and enhanced signal-to-noise ratio. It consists of two 455-bit shift registers A and B. Each shift register can be used alone or in series to form a 910-bit shift register as needed. Each shift register has its own signal injection terminal, signal output terminal, and clock and sampling pulse input terminal. The device is driven by a single-phase clock and the input and output of the sampling pulse acquisition signal. Therefore, the output signal is discrete in time and analog in amplitude, and has the characteristics of digital and analog signals. The device has a signal bandwidth of 5MHZ, a gain of 3-6dB, and a signal-to-noise ratio of 55-60dB. It is an ideal device for sampling and signal processing. Its pin functions are shown in Table 1, the timing diagram is shown in Figure 4, and the circuit diagram is shown in Figure 5.

4 Video accumulation circuit design
Figure 6 is a schematic diagram of the video accumulator circuit designed with CCD321. The two shift registers A and B of CCD321 are used in series to form a 910-bit shift register. The video signal should be delayed by one radar transmission pulse cycle Tr after passing through the 910-bit shift register. Therefore, the shift clock and sampling pulse frequency are Under the conditions of radar transmission pulse frequency of 300Hz and transmission pulse width of 10μs, the shift clock and sampling pulse frequency added to the charge coupled device are, f=910×300=273KH. The number of sampling times within the transmission pulse width is n=10×10-6×273×l03=273. Therefore, the sampled storage signal at this sampling frequency satisfies the Nyquist sampling theorem. As shown in the figure, the transfer clock and sampling pulse generation circuit is composed of ICIA, ICIB, ICIC, IC2A, IC2B and quartz crystal, and TNI21 is a sampling pulse shaping circuit. The video detection signal is added to the sample-and-hold circuit through the voltage follower IC3A. The sampling and holding circuit is composed of IC5 and holding capacitor C1. The sampling and holding circuit samples the input video signal to make the through signal and the delayed signal have the same amplitude-frequency characteristics. The signal sampled by IC5 is sent to one input end of the adder IC3B. The output of the adder is divided into two paths: one is sent to the input end (pin 3) of CCD32l for delay, and after 910 bits of delay, it is output from the 15th pin, and then sent to the voltage follower IC4A after voltage division by W1 and R6. The output of the voltage follower feeds the signal back to the other input end of the adder to realize the addition of the delayed signal and the non-delayed signal. Among them, W1 and R6 are set to ensure that the feedback coefficient β1 is less than 1. The other output of the adder is sent to the voltage follower IC4B. The voltage follower acts as an isolation, and its output is the video accumulation signal.

5 Matters needing attention in the experiment
(1) Customize a quartz crystal with an oscillation frequency of f0 = 273KHz and high frequency stability. The DC voltages of the 4th, 12th and 14th pins of CCD32l must be correct. Vcc is powered by a +12V power supply, and the transfer clock and sampling pulse are TTL level and the waveform must be regular, otherwise the leakage current during sampling will be large and the sampling "leakage clock" interference cannot be eliminated.
(2) Disconnect the circuit from the radar video detector output and the video input, and then connect them to the circuit shown in Figure 6 respectively. The input signal must be ensured to be less than 1VP-P.
(3) The power supply circuit must be decoupled and the ripple must be small. The digital ground and analog ground must be set separately, otherwise it is easy to cause mutual crosstalk.

6 Conclusion
The radar video accumulation circuit designed with CCD321 can improve the radar's signal-to-noise ratio, improve the radar's detection capability and increase the detection distance. After testing, the video detection output signal is 0.4V, the noise is 0.3V, and the signal-to-noise ratio is Si/Ni≈1.33. After the video accumulation circuit, the output video signal is lV, the noise is 0.5V, and the signal-to-noise ratio is Soi/NoN≈2. Therefore, the signal-to-noise ratio is improved by 20(1g2-1g1.33)≈3.5db.