Embedded test solutions and high-speed test technology

Preface

At present, SOC technology has become the main research direction in many application fields, such as processors, mobile phones, modems and other products. This type of SOC chip integrates digital logic circuits, analog circuits, memory modules and intellectual property (IP) cores, and even includes microprocessors, peripheral interfaces and communication modules in one chip. The application of SOC chips is of great help in improving system performance, reducing system energy consumption, reducing system electromagnetic interference and improving system integration, and conforms to the trend of thin and short products.

The 93000 SOC test system launched by Agilent fully meets the needs of the industry and provides effective solutions for high-speed digital circuits, embedded memory and mixed signal testing.

Embedded memory testing Embedded memory is an indispensable part of SOC chips, so its testing and analysis methods are also very important. In the memory test, the 93000 SOC test system does not require additional hardware, and can directly use the high-speed digital test channel as memory test to achieve the purpose of full-speed testing. At the same time, switching logic and memory tests during operation can effectively improve productivity and further perform redundancy analysis and repair.

Embedded Memory Testing

Embedded memory is an indispensable component of SOC chips, so its testing and analysis methods are very important. The 93000 SOC test system does not require additional hardware for memory testing. It can directly use high-speed digital test channels as memory tests to achieve full-speed testing. At the same time, switching between logic and memory testing during operation can effectively improve productivity and further perform redundancy analysis and repair. [page]

Memory testing and debugging

First, in the APG (Algorithmic Pattern Generator) software provided by 93000, we can describe the size of the memory to be tested, including the number of addresses in the X and Y directions, the number of I/O bits and their relationship with the physical address, which is the so-called irregular pattern. Because the independent channel architecture of the 93000 SOC system can use 1024 test channels at will in resource arrangement, there is almost no limit on the number of I/Os, and therefore it is more flexible in DUT board design and pin arrangement. When the object to be tested has multiple memory blocks, or for embedded memory, only some pins are used for memory testing, the function of defining multiple test ports in APG can be used to assign different pins to different test ports. However, it is still necessary to define the access operations, such as read and write, and whether multitasking or pipeline processing is required in these operations.

Then it is necessary to select the test pattern, the purpose of which is to use a series of read and write operations to repeatedly test each unit of the memory. Different patterns can detect different process errors, such as fixed errors, coupling errors, etc. 93000 has made standard memory test patterns such as check plate and step 6N into a library. Users can directly select them, or edit them in ASCII format according to the specific needs of the object under test.

The memory test patterns need to occupy a large amount of vector memory. For example, if a 12×12 256Mb SRAM is stepping 6N, it takes about 10M cycles to scan all addresses, and this does not include vectors for other functional tests. If a 93000 test system with an independent channel architecture is used, the use of software APG can greatly compress the system memory usage to 1/19,500 of the original, that is, about 536 cycles. Therefore, when testing multi-functional SOC chips, there is no need to worry about increasing the system's memory resources because of adding memory testing.

Due to its different circuit architecture, memory modules require special debugging tools to observe where the problem is with the object under test. 93000 provides two debugging tools for memory testing: bitmap and error storage. In addition, status lists, oscilloscopes, and timing diagrams can also be used as auxiliary tools.

Redundancy patching

With the emergence of high-capacity memory, it is impractical to discard the entire memory block as long as there is a fault. Usually, for SRAM/DRAM above 2Mb, extra rows or columns can be added to the module, and the fault point can be bypassed by laser. As for whether the limited rows or columns are sufficient to repair the fault, it must be judged by the test system.

General memory test systems have their own algorithms to judge whether it is sufficient to repair, but it is difficult to say whether it is optimized, especially when the object to be tested is relatively simple. 93000 provides a dynamic redundant judgment. When a fault point is found, its address and I/O data will be sent back to the judgment program edited by C for processing. If it can still be repaired, the test work will continue. Otherwise, it is known that the chip has no remaining rows or columns to use. When it is found that there are still faulty addresses, indicating that it cannot be repaired and must be discarded, other points can be skipped and another item can be tested directly or jump to the next chip to save test time.

The Challenges of High-Speed ​​Testing

The 93000 SOC system also has a complete solution for testing high-speed digital circuits. At present, the P series products of the 93000 SOC have test capabilities of 600MHz, 800MHz and even 1GHz, and its NP series products have test capabilities of up to 10GHz, which fully meet the test requirements of high-speed CPUs and network processors. However, the test of high-speed circuits not only requires the capabilities of the test system, but also puts higher requirements on the entire test environment.

Generally speaking, we will first face the problem of transmission lines. Different materials of transmission lines have different relative capacitance and inductance characteristics. In a low-speed transmission environment, the capacitance effect and inductance effect of the transmission line itself will not have much impact on the transmitted information, but in a high-speed transmission environment, the capacitance effect and inductance effect cause the distortion of the transmitted information. Whether in the data transmission inside the chip or in the application outside the chip, we can foresee the importance of the material and electrical characteristics of the transmission line itself in a high-speed environment.

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The chip test environment includes several main factors, such as the test system, supporting equipment such as the chip feeder/load board or probe/probe card and the chip itself. During the entire test process, the test system sends out the relevant test vectors, passes through the load board/probe card to the chip input, and then receives the results sent by the chip output after the internal logic operation of the chip to determine the correctness of the test. This process seems simple, but in a high-speed environment, the interface between the test system and the supporting equipment or the interface between the supporting equipment and the chip will cause impedance matching problems due to the degree of fit of the contact points or the different electrical characteristics of each other. In order to achieve impedance matching, matching circuits can be used between each interface to compensate for the impedance characteristics on both sides of the interface. If one side is an open end, a terminal resistor needs to be added to the end to avoid total reflection of the signal.

In various test systems, round-trip delay (RTD) is a feature due to the connection between the system itself and the chip. In order to ensure that the chip is not affected by the transmission delay, the system itself can verify that the signal is sent to the chip input in advance, or delay the comparison of the signal sent back from the chip output to compensate for such an impact. However, if this phenomenon occurs on an I/O channel, when the driving signal and the comparison signal occur too close in time, this compensation is ineffective. This situation of signal conflict on the transmission line is called bus contention, which is more likely to occur in high-speed transmission tests. In order to avoid this situation, the diagram code and timing of the test program can be considered, and the signal comparison before the driving transmission signal can be changed to be ignored or the time setting of the two can be separated by at least one RTD time. At the same time, it is best to discuss with the chip designer to ensure error coverage.

The tolerance range of high-speed digital signal testing is relatively small, so comprehensive consideration is required in the formulation of test conditions and test environment. The material and routing of the load board or probe card, the accuracy of the test system, the architecture of the system itself, or the electrical characteristics of the chip itself, etc., must be fully evaluated at the beginning of building the relevant test environment.