TMS320F2812 Data Acquisition System with GPS Timing

Nowadays, there are many data acquisition systems, some are designed based on digital signal processors DSP, and some are designed based on field programmable gate arrays FPGA. Although these acquisition systems have good data acquisition and processing capabilities, most of them use traditional timing modes.

Remote synchronous measurement is a method often used in engineering. If the traditional timing mode is used, the clock frequency is generated by crystals, which will age and be easily affected by changes in the external environment and long-term precision drift, resulting in a decrease in timing accuracy. In this way, the data of remote synchronous measurement is no longer synchronized and simultaneous in theory. This system adopts a new GPS timing method, and the data acquisition system designed in combination with DSP technology and USB communication technology can better solve this problem.

1 Overall hardware composition and working principle of the data acquisition system

The data acquisition system consists of analog input, synchronous sampling control, A/D conversion, microprocessor and interface, as shown in Figure 1.

The analog input part is equipped with multiple channels (such as 16 channels), which can be used to measure several voltages and currents simultaneously. The voltage or current from the secondary side of the PT or CT is sampled by the synchronous sampling system based on the GPS time reference after isolation transformation and analog low-pass filtering, and is sequentially placed in the fixed RAM area after A/D conversion. According to the recursive DFT algorithm, the DSP calculates all the measured fundamental components of each phase at each new sampling point, and then uses the time information provided by the GPS receiver serial port and the sequence number of the first sampling point in the data window to set a "time tag" for easy identification of the calculation result. The calculated phase quantities together with their time tags are sent to the PC host computer for processing and analysis through the DSP bus and USB2.0 data line in a certain data format.

2 Synchronous sampling control unit based on GPS timing

Synchronous sampling is the key technology to achieve remote synchronous measurement. Only when the sampling of each measurement point is synchronous and the phasors calculated at the same time have a unified reference time benchmark, their phase relationship can be directly compared. This paper discusses six different timing methods: radio broadcast, LORANC, OMEGS, GOES, GLO-NASS, and GPS. The error comparison of these timing methods is listed in Table 1.

By comparison, it is not difficult to see that the traditional clock synchronization method is difficult to meet the requirements of remote synchronization measurement in terms of accuracy and practicality due to the influence of technical and economic factors; only the superior performance of the GPS precision timing method can meet the requirements. Therefore, this article introduces a new clock synchronization method based on GPS time signal.

2.1 Introduction to GPS System

GPS (Global Positioning System) is a second-generation satellite navigation system developed by the United States. The GPS system consists of a space segment, a ground control segment, and user equipment. The space segment is mainly composed of 21 working satellites and 3 backup satellites. At least 3 satellites can be seen anywhere on the earth (with a 360° field of view) (based on the author's actual use). The ground control segment includes monitoring stations, master control stations, and injection stations. The user equipment is the GPS receiver. The receiver selected for this system is the GPS-OEM board (model GPS15L, which will be discussed in detail in Section 2.3). It calculates the location of the receiver (antenna) and the GPS time based on its own clock and the received navigation message. [page]

2.2 GPS Timing Principle

The current timing GPS receiver, after its internal clock is synchronized with GPS time, will provide a 1 pps (pulse per second) signal synchronized with UCT time and its corresponding time code, as shown in Figure 2.

2.3 Synchronous Sampling Control Unit Hardware

When designing this module, the GPS15L OEM board and the MCU AT89C51 developed by Garmin were selected as the GPS receiver and controller respectively. This module embodies the GPS timing technology to be used in the entire system. The working principle is as follows: After the system is powered on and reset, the MCU initializes the GPS15L board through the serial port TXD and sets the data format transmitted by the GPS receiver. After the initialization is completed, the GPS15L board will give the corresponding information. After the MCU recognizes this information, it starts to receive the time data transmitted by the GPS15L board, processes it, and converts it into Beijing time for output. As shown in Figure 3, the serial ports RXD and TXD of the MCU AT89C51 are connected to the TXD1 and RXD1 of the GPS15L board respectively for communication. Since TXD must send an initialization command to the GPS15L board when powered on and transmit Beijing time after initialization, in order to prevent the two stages of work from affecting each other, the P1.0 port line and several logic gates are used to control the order of communication. After the GPS15L board is initialized, it will also output a second pulse signal. One of the 1pps signals is used as an external interrupt source of the microcontroller to achieve synchronous processing of time information, and is also used to monitor whether the signal is normal. Another signal can be controlled by the microcontroller P1.1 port to determine whether it needs to be transmitted to the next level controller based on the monitoring results.

In addition, the high-stability crystal oscillator used in this circuit is an OCXO type stable crystal oscillator, whose operating frequency is 1 MHz and the frequency difference is no more than 10-7. The oscillation signal it outputs is shaped and level-converted to a level suitable for TTL circuits, and after frequency division by a counter, a clock signal that meets the sampling rate requirements is obtained (the sampling rate is adjustable). The clock signal is synchronized once every 1 s by the rising edge of the 1 pps signal, so that it runs on the GPS time reference. Since the 1 MHz crystal oscillator has a high stability and the drift within 1 s does not exceed 1 μs, the obtained synchronous sampling pulse has a high accuracy.

3 Interface between ADC and DSP

The DSP chip uses the digital signal processor TMS320F2812 developed by Texas Instruments, USA. It is a 32-bit fixed-point operation, highly integrated, and cost-effective DSP chip.

The data acquisition system uses ADS8361 as the off-chip ADC module. Although TMS320F2812 has a 16-channel 12-bit ADC, in order to further improve the A/D conversion accuracy of the system, an off-chip peripheral ADS8361 is added. ADS8361 is a 2+2 channel, 16-bit A/D converter; it is fully compatible with ADS7861 (12-bit) and can be directly interfaced with the F2812 digital signal processor. It is divided into two groups by four-channel differential input and connected to independent converters respectively, which can complete the simultaneous acquisition of dual signals, and the maximum conversion rate can reach 500 kHz. It has strong anti-interference ability when working at a frequency of 50 kHz, which is particularly suitable for occasions with high sampling rate requirements for data acquisition. In addition, ADS8361 also provides a high-speed dual serial interface, which can effectively reduce software overhead, and the power consumption is very low, only 150 mW.

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3.1 ADS8361 and TMS320F2812 interface circuit design

The TMS320F2812 processor provides a multi-channel buffered serial port (McBSP) and a serial peripheral interface (SPI), both of which can be interfaced with the ADS8361. According to the design requirements, this system uses the McBSP interface expansion method. When designing the interface hardware between ADS8361 and TMS320F2812, in order to avoid ringing of the data signal, it is considered to add an absorption resistor between DSP and ADS8361. Since TMS320F2812 has only one McBSP interface, ADS8361 must be set in mode 2 and mode 4. The hardware interface circuit of TMS320F2812 and ADS8361 is shown in Figure 4. The CLOCK, (RD+CONVST) and SDA pins of ADS8361 are connected to the CLKX, (FSX+FSR) and DR pins of McBSP respectively. Since only one A/D converter chip is connected to the McBSP, the chip select signal (CS) is directly grounded. If multiple A/D converter chips need to be expanded, GPIO can be used to control the chip select signal. At the same time, general I/O is used to control the working mode of ADS8361, so that M0=0 and M1=1; DX controls the channel selection of ADS8361.

3.2 Design of analog input signal conditioning circuit

The phase current and phase voltage of the power system are transformed by CT and PT respectively, and then output as standard ±10 V analog voltage signals. This analog voltage signal needs to pass through the low-pass filter at the front end to filter out unnecessary high-frequency noise signals and transform the analog input signal range from ±10 V to the signal range acceptable to the back-end A/D. The analog conditioning circuit of each channel is shown in Figure 5.

4 USB interface communication circuit part

The communication circuit uses a USB interface, and the USB interface chip uses Cypress's CY7C68001. The connection circuit between CY7C68001 and TMS320F2812 is shown in Figure 6.

As a peripheral of TMS320F2812, CY7C68001 uses asynchronous memory interface to connect with TMS320F2812. The host PC can wake up CY7C68001 and configure USB chip. USBCS is the chip select signal line of CY7C68001. When USBCS is low, CY7C68001 uses asynchronous read and write mode to complete the data and command exchange between the two.

CY7C68001 has two external interfaces, namely FIFO data interface and command port. The data acquisition system configures these two external interfaces in the space with address range of 0x004000～0x004004, and the allocation is listed in Table 2. TMS320F2812 can access the data in 4 1 KB FIFOs through the FIFO data interface of CY7C68001, and the selection of FIFO data interface is realized by controlling address line A[2:0]. When the address line A[2:0] of TMS320F2812 is 100B, the command port of CY7C68001 is selected, and then 37 registers, Endpoint0 buffer (64-byte FIFO) and description table (500-byte FIFO) can be accessed through the command port. If the Endpoint0 buffer and description table are also regarded as registers, then a single command port contains a large number of registers, and read/write access to these registers adopts a secondary addressing method, that is, first write the register sub-address and operation type (read operation or write operation) to be addressed through the command port, and then read or write the data to the corresponding register through the command port.

CY7C68001 also has an interrupt signal USBINT and four status signals (USBREADY, FLAGA, FLAGB, and FLAGC). The interrupt signal USBINT occupies the external interrupt XINT1 of TMS320F2812, and the status signals USBREADY, FLAGA, FLAGB, and FLAGC are configured in another extended register, which TMS320F2812 can query to obtain the USB status. The WAKEUP of the USB chip is also configured in another extended register, and TMS320F2812 achieves the purpose of waking up the USB by writing to this register.

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5. Software part of the system

The software part of the system includes the main program and each interrupt program as well as the USB communication program between the system and the host PC. The main program completes the initialization of each variable and serial port, and uses the Fourier transform algorithm to calculate the real and imaginary parts of each sampling point. The interrupt program includes the A/D conversion program, the GPS time information reading program, etc. This article focuses on the design ideas of the interrupt response program for reading the serial port output of the GPS receiver. The program flow is shown in Figure 7.

6 Power Supply Design

The power supply circuit adopts a derating design and uses a high-precision power supply circuit to ensure the reliability of the power supply system.

① The internal reference power supply of ADS8361 is +2.5 V.

② The power supply voltage of the GPS15L OEM board is 3.3~5.4 V, and the power supply voltage of the GPS receiving antenna is 3.0 V.

③ TMS320F2812 requires dual power supplies (1.9 V and 3.3 V) to power the CPU, Flash, ROM, ADC, and I/O interfaces.

When powered on, in order to ensure the correct reset of each module in the chip, the power supply of TMS320F2812 needs to meet a certain timing. The system first powers on all +3.3 V power pins (VDDIO, VDD3VFL, VDDA1, VDDA2, VDDREF), and then connects the 1.9 V (VDD, VDD1) chip core power supply; when the voltage of VDDIO rises to 2.5 V, VDD rises to 0.3 V, so as to ensure that each module in the chip can be correctly reset when powered on. When powered off, the system resets before VDD drops to 1.5 V. This ensures that the Flash module in the chip is correctly reset before VDD and VDDIO are powered off. In the design of this system, the dual-power output, Low-Dropout power supply TPS76801QDR provided by TI is selected to power the TMS320F2812 to achieve the above power supply timing.

Conclusion

This data acquisition system has four channels, and the A/D conversion accuracy is 16 bits. It has high conversion accuracy and strong anti-interference ability. It can transmit the collected data in real time through USB. In addition, the most important thing is that the GPS timing mode replaces the traditional timing mode, which is particularly suitable for occasions that require remote synchronous acquisition. For example: in the electrical parameter parameters of high-speed electrified railways, in order to synchronously obtain the train current, position, rail potential, rail current, and suction line current, it is only necessary to use the same data acquisition system at two measurement points on the train and the rail ground at the same time, so that the measured phasor data has a unified time base, which is convenient for scientific analysis of these parameters.