Design of Power Quality Monitoring System Based on NiosⅡ

In the power system, to realize the real-time monitoring and recording of various parameters of power quality, it is necessary to collect and process the electric energy at high speed, especially for the analysis and calculation of each harmonic of power quality. The system needs to complete a large amount of calculation and processing work, and at the same time, the system needs to realize the communication, control, human-machine interface and other functions with the external system. However, most of the power quality monitoring systems are based on the hardware and software platform structure with microcontroller or (with) DSP as the core and the corresponding design and development mode, which have the disadvantages of insufficient processing power, poor reliability, and difficulty in upgrading. This paper applies SoPC technology to the power field and embeds a 32-bit NiosⅡ soft core system in FPGA. It can realize the functions of collecting, processing, storing and displaying electric energy signals, and realize the requirements of real-time system.

1 System Overview
1.1 Basic Principles of Power Quality Detection System
Power quality monitoring mainly monitors and records various power quality parameters in real time. Its functional process is: the voltage and current in the power grid are converted into -5~+5V voltage signals and 1~2mA current signals through PT and CT, and then sampled after pre-processing. The sampled values ​​are processed, and the processing results can be stored in the data storage unit or communicated with the computer terminal through the communication module. The processing results can be controlled and viewed as needed. The basic principle block diagram of the system is shown in Figure 1.

1.2 Algorithm Introduction
This paper uses the radix-2 DIT FFT algorithm to process harmonic data. The input of the butterfly diagram of the traditional radix-2 algorithm is arranged in the order of the code bits being reversed, and the output is in natural order. The position of the input data of the butterfly at different levels at the same position is not fixed, which makes it difficult to achieve loop control and difficult to implement in parallel when programming with FPGA. By analyzing the traditional radix-2 butterfly diagram and adjusting the position of its rotation factor, the butterfly diagrams at each level are made consistent, as shown in Figure 2, and loop control can be achieved.

The input of this structure is sequential, while the output is bit-inverted. The rotation factors of each level are placed in the FPGA's on-chip ROM. The addressing of the adjusted rotation factors has a certain rule. For an N-point FFT (N=2k, K is the number of levels), there are, ..., N/2 rotation factors in total. They are arranged in reverse order of the bit code into an array containing N/2 elements, denoted as:,, then the rotation factors of the i-th level (i=O.1, 2, ..., K-1) are arranged in the order of W(O), W(1), W(2), ..., W(2i) repeated 2k-il times. Its characteristic is that the order of input and output data of each level is unchanged, so the geometric structure of each level is fixed. This structure is convenient to address and easy to program with FPGA to realize the internal parallel FFT hardware structure, thereby significantly speeding up the operation speed of FFT. [page]

2 Hardware Design of Power Quality Detection System
2.1 A/D Converter
According to the measured data, if a 12-bit resolution A/D conversion chip is used, it will cause at least 1.67% error for the 15th harmonic, and in actual harmonic measurement, 30th or more harmonics are generally measured. Therefore, the resolution of the A/D converter in the field monitoring unit should be guaranteed to be 14 bits or above. This paper uses AD73360 as the analog-to-digital conversion chip of the sampling system. Its six input channels can be divided into three pairs to correspond to the three phases in the power system. The chip can sample six channels of signals at the same time at sampling rates of 8 kHz, 16 kHz, 32 kHz, and 64 kHz. AD73360 can meet the device's requirements for high-speed sampling. The connection between AD73360 and FPGA is shown in Figure 3.

2.2 NiosⅡ soft-core processor
The SoPC based on 32-bit RISC embedded soft-core NiosⅡ has unparalleled advantages over other SoPCs (such as FPGA embedded IP hard-core SoPC). With the NiosⅡ soft-core processor, users will not be limited to general processor technology but will tailor and customize the processor according to their own standards, select appropriate peripherals, memory and interfaces as needed, and easily integrate their own proprietary functions, such as DSP, user logic, etc. This is very conducive to the design of high-order harmonics, which are computationally intensive and have complex control logic.
In order to meet future performance requirements, the power quality monitoring system should be able to be improved and upgraded at any time. Multiple NiosⅡCPUs, customized instruction sets, hardware accelerators, etc. can be added to achieve better performance goals. The system performance can also be adjusted through the Avalon switching architecture, which supports multiple parallel data channels to achieve high-throughput applications.
2.3 Hardware system platform design
Figure 4 is a hardware structure block diagram of the entire system. The system mainly consists of:

(1) The core module of the system adopts the STRATIX series EPlS25 type FPGA, which contains: 10 DSP modules, 25,660 logic units, 48 ​​embedded multipliers, a total RAM of up to 1,922,576 bits, 6 digital phase-locked loops, and up to 702 available I/O ports. It is a PLD device with a high-performance structure system, combining powerful core performance, large memory, DSP function, high-speed I/O and modular design. Its embedded DSP module provides data processing capabilities higher than the DSP processor and can complete the more resource-intensive multiplier unit. These resources are more than enough for a power quality monitoring system.
(2) The NiosⅡ soft-core processor is the CPU of the entire system module, and its specific characteristics have been described in detail above. In addition to coordinating and controlling various hardware devices, the NiosⅡ soft-core processor also executes software algorithms for power parameter-related data.
(3) The Avalon switch bus is automatically generated by SoPC Builder. It is an internal bus used between the system CPU and peripherals. The disadvantage of the traditional bus structure is that only one host can access the bus at a time, resulting in a bandwidth bottleneck. In the Avalon bus structure, the bus host does not preempt the bus itself. The Avalon switch structure can realize seamless data transmission between peripherals and the best performance data channel, and it also supports user-designed off-chip processors and peripherals.
(4) The harmonic analysis module uses the embedded DSP to process the collected 16-bit digital signal, input the processing algorithm program of the power metering index parameters, and temporarily store the results in the on-chip memory. Finally, the NiosⅡ soft core control unit completes data transmission and human-computer dialogue through the RS 232 or RS 485 serial port. Harmonic is a periodic sinusoidal wave component whose frequency is an integer multiple of the fundamental frequency. There are many methods for harmonic transformation. This paper uses FFT to complete the detection of voltage RMS, current RMS, active power, reactive power, apparent power, frequency, power factor and steady-state harmonic components.
The above is a hardware platform for a basic power quality monitoring system based on NiosⅡ proposed in this paper. According to different requirements, measures such as adding DMA and custom modules to the core modules of the system can also be taken to form a more functional power quality monitoring system. [page]

3 Software Design of Power Quality Detection System
3.1 SoPC Builder Design
According to the hardware platform structure of the system, add NiosⅡProcessor and select it as fast type to ensure the speed performance of the system. Then add SPI, PIO, Character LCD, FLASH Memory, Avalon Tristate Bridge, SDRAM Controller, On chip Memory, DSP, timer and other modules. After setting the parameters of the modules, click the two options in the System control to actively assign addresses and interrupts to each module. Then select Reset Address as FLASH and Exception AddFess as SDR-AM in NiosⅡMore "CPU" Setting. Finally, click Generate to generate the corresponding ptf file. In this way, the SoPC Builder design of the system is basically completed.
3.2 NiosⅡIDE Design
After entering NiosⅡIDE, create a new application project, select ptf file and Black Project, and a blank application project based on the existing SoPC is established. Then make necessary project settings in System Library. Then fill the C program of the power parameter algorithm into the project, and then compile and debug the software. After debugging, all programs and executable files are downloaded to the FPGA. At this point, a NiosⅡ-based power quality monitoring SoPC design is completed.

4 Result Analysis The
power quality test results mainly include harmonic analysis data of current and voltage, electric power measurement data, supply voltage measurement data, frequency measurement data, three-phase unbalance measurement data, flicker measurement data and error analysis. It can be seen from the measured data that due to the widespread use of various nonlinear power electronic devices, the content of high-order harmonics has increased. Taking the harmonic analysis data of three-phase voltage as an example, the harmonic content rate of the 2nd to 30th harmonics, that is, the ratio of the effective value of the nth harmonic to the effective value of the fundamental wave, is obtained, as shown in histogram 5.

In Figure 5, the three consecutive columns represent the voltage harmonic content of phase A, phase B, and phase C. It can be seen that the harmonic content of odd-order harmonics is significantly higher than that of even-order harmonics, among which the 3rd, 5th, 7th, 9th, 11th, and 13th harmonics are the most obvious, and the corresponding harmonic content of the three-phase voltage of A, B, and C is similar, except that the 9th and 13th harmonic content of phase B is slightly higher than that of phase A and phase C. The harmonic content should be reduced as much as possible, such as starting from the power supply voltage, line impedance, load characteristics, etc., to reduce the content of high-order harmonics.

5 Conclusion
This paper proposes a design scheme for a power quality monitoring system based on NiosⅡ, which can realize the functions of collecting, processing, storing and displaying power signals, and meet the requirements of real-time systems. However, due to limited experience and technology, the system needs to be improved in some aspects. For example, how to further reduce the harm of three-phase unbalance and flicker. This system takes advantage of the configurability. Interested friends can fill, modify and improve it according to their specific needs on this basis to obtain a better power quality monitoring SoPC.