Design of a Frequency Characteristic Tester

The frequency characteristics are measured by frequency sweeping. The frequency sweeping signal is generated by AD9851, which can generate a sine wave with pure spectrum, wide frequency range and very high stability. The frequency response characteristics are measured by diode negative feedback bridge limiting amplifier circuit and effective value sampling circuit, and finally the amplitude-frequency characteristics and phase-frequency characteristics of the measured network are displayed by oscilloscope.
A feature of this system is that more serial chips (AD9851, TLV1544 and TLV5638) are used. In order to make the signal in the circuit clean, the circuit connection should be reduced. The use of serial chips can effectively simplify the circuit, ensure the stability of the circuit and reduce signal noise. However, since the serial chip sacrifices the time efficiency of the program, the program structure should be designed reasonably.

1 System solution demonstration and selection
1.1 Design and demonstration of amplitude measurement circuit
Solution 1: Peak detection circuit. The basic peak detection circuit is composed of a diode circuit and a voltage follower, which is realized by charging and discharging a capacitor. This circuit has a large ripple when measuring low-frequency signals, which is suitable for measuring signals in the medium and high frequency bands.
Solution 2: True effective value detection. According to the working principle of true RMS detection, it can be divided into linear RMS detector, logarithmic RMS detector and digital RMS detector. The typical true RMS conversion chip is AD637. When using AD637 to measure signals with a peak factor of up to 10, the additional error is only 1%, and there are few peripheral components and wide bandwidth.
In summary, option 1 is selected.
1.2 Design and demonstration of phase measurement circuit
Option 1: Waveform analysis method. Two high-speed A/D conversion chips are used to sample the two input signals at equal time intervals and store the sampling results separately, and then analyze the waveform data of the measured signal. Scan the waveform data stored in RAM and calculate the time interval between the maximum or minimum values ​​of the two A/D converters to collect the two parts of the waveform data. The phase difference of the signal is: φx=(Tx/T)x360°, where Tx is the time interval between the two signals' adjacent extreme values, and T is the signal period.
Option 2: Counting method. After the two measured signals pass through the XOR gate, a phase detection pulse signal is generated and sent to the FPGA for counting. The count value is N. If the signal frequency is, f, and the counting frequency is fclk, then the phase difference is: φx(Nf/fclk)x360°, which can determine whether the measured signal is ahead or behind the standard signal. Since the phase difference is symmetrical between 0°~180° and 360°~180°, the count value after XOR is the same, so a polarity judgment circuit is required. The phase polarity judgment circuit can be implemented by a D flip-flop. The two signals are connected to the D and CP terminals of the D flip-flop. The high and low levels output from the 0 terminal can determine the polarity of the phase difference.
Scheme 1 requires software to process a large amount of waveform data to achieve high accuracy, and the acquisition time interval is difficult to accurately control. It is mainly suitable for situations where the accuracy requirements are not very high. The measurement process of Scheme 2 can be fully implemented by FPGA. The signal frequency f generated by AD9851 is known and there is no need to measure the frequency, so this method is very easy to implement. In addition, the FPGA's 40 M high-frequency crystal oscillator is used to count, and the measurement accuracy and measurement range are improved. Therefore, Scheme 2 is adopted.

2 System overall design and implementation block diagram
This system is based on a single-chip microcomputer and FPGA, and consists of a frequency sweep signal source module, a peak detection module, a limiting amplifier module, and a phase measurement module. The system block diagram is shown in Figure 1. In order to improve efficiency, chip control is mainly implemented by FPGA, and the single-chip microcomputer only provides trigger signals for each module of the system. When the system is working, AD9851 generates a sinusoidal signal of a certain frequency. After passing through the network under test, its amplitude and phase will change. The output end of the network under test passes through the AD637 effective value detection circuit to obtain the true effective value of the signal, and the A/D sampling is sent to the single-chip microcomputer. At the same time,
the signals before and after the network under test are shaped into a square wave with a peak-to-peak value of +5 V by the limiting amplifier module, and sent to the FPGA for phase measurement. Then change the frequency of the signal generator, measure the phase difference and amplitude value of the corresponding frequency point, until the test of the entire frequency band is completed, and finally the amplitude-frequency characteristic and phase-frequency characteristic curves of the network under test are displayed by an oscilloscope.

3 Main Function Circuit Design
3.1 Sweep Signal Generator
AD9851 is a highly integrated direct digital synthesizer produced by AD using advanced CMOS technology. It can be used directly as a signal source, or converted into a square wave output through its internal high-speed comparator as a sensitive clock generator. It integrates phase accumulator, waveform memory, and 10-bit high-speed D/A in one chip, with wide bandwidth, high frequency accuracy and stability, and simple peripheral circuits.
Its internal structure is shown in Figure 2. The control word register inside AD9851 first stores the frequency and phase control words from the outside. After the phase accumulator receives the data from the control word register, it determines the final output signal frequency and phase, and then passes through the internal D/A converter to obtain the final digital synthesized signal. [page]

Assume that the number of bits of the phase accumulator is N, the value of the phase control word is FN, the number of bits of the frequency control word is M, the value of the frequency control word is FM, and the internal working clock is Fc. The frequency and phase of the final synthesized signal can be determined by the following formula: F=Fc·FM／2N, θ=2πFN／2M. Where M=32, N=5, the external input clock of 25 MHz, after internal 6 times frequency multiplication, is fc=150 MHz. Since there is no need to set the phase, the five-bit phase control word is always written as 0, and the frequency control word is FM=2NxF／Fc.
3.2 Effective value detection module
The true effective value detection circuit uses AD637 of ADI Company. The chip directly outputs the effective value voltage of the signal according to the true effective value calculation formula. The schematic diagram is shown in Figure 3. By using the on-chip post-filter network, the in-band ripple can be effectively reduced. A 1μF capacitor is connected to the C_AV port. When the input signal frequency is less than 1MHz, the amplitude measurement error is less than 1%. The accuracy is very high.

3.3 Limiting amplifier circuit
Before measuring the phase of the signal, it must be shaped into a square wave. However, when the amplitude of the signal changes greatly after passing through the measured network, it may exceed the measurement range of the post-processing chip when the signal is strong, and cannot be recognized by the post-processing chip when the signal is weak. Since the measurement of the frequency or phase of the signal only requires knowing its period information, not the amplitude information, in the module that shapes the sine signal into a square wave, limiting amplification is adopted instead of a simple LM311 shaping circuit to achieve better results.
The specific circuit is shown in Figure 4. This limiting amplifier circuit consists of three parts: the front-stage in-phase amplifier, the limiting amplifier and the level conversion circuit. The front-stage in-phase amplifier circuit mainly plays the role of impedance transformation; the limiting amplifier circuit uses the diode 1N4148 to realize negative feedback bridge limiting. If the output signal amplitude is greater than 5 V, the diode of the bridge circuit is turned on, the voltage regulator diode works, and the voltage is clamped at about 5 V; the level conversion circuit shapes the amplified signal into a square wave signal after comparison. Converted to TTL level for easy processing in subsequent circuits.

Since the input and output voltages of the first level of the comparator are very large, the op amp chip in the circuit should be an op amp with ultra-high slew rate, large output current, and high voltage resistance. At the same time, in order to make the signal entering the comparator more stable, an op amp with a large gain-bandwidth product should be selected. Taking all the above factors into consideration, LF356 is selected. Its gain-bandwidth product reaches 5MHz and the slew rate is 12V/μs, which far meets the design requirements. [page]

4 System software design
The system software design part is based on the single-chip microcomputer and FPGA as the platform, and completes the functions of keyboard input, amplitude measurement, phase measurement and oscilloscope display of swept frequency signal. The keyboard input sets the sweep frequency range and frequency step. The amplitude measurement is realized by the 10-bit serial AD/C TLV1544, and the phase measurement is counted by the 40 M crystal oscillator, with high measurement accuracy. The measurement data is stored in the RAM of the FPGA and output through the dual-channel TLV5638. The system provides two display modes, one is to display the amplitude-frequency and phase-frequency curves of the entire measured network through an oscilloscope, and the other is to display the amplitude and phase of a specific input frequency through an LCD. Since the AD9851, TLV1544 and TLV5638 used in the system are all serially controlled, the program is somewhat complicated and the timing needs to be strictly controlled, otherwise problems are prone to occur. At the same time, considering the time efficiency of the program, redundant code should be avoided, and multiplication and division operations should be avoided when shift operations can be used. The swept frequency measurement process is shown in Figure 5.

5 Test methods and results
In order to verify the performance of the frequency characteristic tester, a double-T network with a center frequency of 5 kHz is used as the network under test. A certain frequency is manually input, and the amplitude and phase corresponding to the frequency point are displayed through the LCD. The amplitude measurement accuracy can reach 5%, and the phase measurement accuracy is 1°. The frequency band range of the sweep signal is set to 1~10 kHz, with a frequency step of 10 Hz. The frequency characteristic curve of the double-T network displayed on the oscilloscope is shown in Figure 6.

6 Conclusion
This system can better complete the function of measuring the frequency response characteristics of a specific network, and the amplitude-frequency characteristics and phase-frequency characteristics can be accurately measured and displayed. The system can automatically step measurements in the full frequency range and specific frequency range, and the measurement range and step frequency value can be manually preset. The LCD displays 5-digit frequency values, 3-digit voltage values, and 3-digit phase values ​​(another digit is displayed as a symbol). The amplitude-frequency and phase-frequency characteristic curves can be displayed simultaneously on the oscilloscope. The entire system is stable, has high measurement accuracy, and flexible human-computer interaction under the organic combination and coordinated control of the single-chip microcomputer and FPGA.