Advantages of SOI Technology and Its Manufacturing Technology

1 Introduction

SOI is the abbreviation of Silicon-On-Insulator, which refers to a material with a structure in which a thin layer of single-crystal silicon is grown on an insulating substrate, or a single-crystal silicon film is separated from a supporting silicon substrate by an insulating layer (usually SiO2).

Initially, SOI materials were developed to replace SOS (Silicon-On-Sapphire) (Note: the insulating substrate is sapphire) materials to make radiation-resistant integrated circuits for space military purposes. Since it was found that thin-film SOI MOSFET has excellent proportional scaling properties, SOI technology has great appeal in deep submicron VLSI applications. Currently, SOI technology is moving towards commercial application, especially in low-voltage, low-power circuits [1-2], high-frequency microwave circuits, and high-temperature radiation-resistant circuits [3].

This article explains the advantages of SOI by comparing the differences between SOI and bulk silicon devices in terms of parasitic capacitance, latch-up effect, hot carrier effect, and radiation effect. It also introduces the three mainstream manufacturing technologies of SOI wafers, as well as their development trends and existing problems in the field of microelectronics.

1.1 Advantages of SOI [4, 5, 6, 7]

SOI structure devices have more advantages than similar bulk silicon devices. Below we take CMOS as an example to compare the two.

The basic unit of CMOS integrated circuit is CMOS inverter, which is composed of an NMOS and a PMOS. As shown in Figure 1, in the bulk silicon CMOS inverter, the PMOS is made on an N-type substrate, while the NMOS is made in a P-well (the P-well is a local P-type material specially made on an N-type substrate using ion implantation technology). The P-well isolates the NMOS and PMOS from each other. In SOI CMOS, the PMOS and NMOS tubes are respectively made in the thin Si layer on the top of the SOI material, and the NMOS and PMOS are isolated from each other. Due to the differences in the structures of bulk silicon CMOS and SOI CMOS, they have great differences in parasitic capacitance, latch-up effect, hot carrier effect and irradiation characteristics.

Figure 1 Cross-section of a CMOS inverter

2.1 Parasitic Capacitance

The parasitic capacitance between the source-drain diffusion region and the substrate of NMOS and PMOS varies linearly with the substrate doping concentration. As the device size decreases, in order to reduce the short channel effect, the substrate doping concentration must be appropriately increased, and the source-drain junction capacitance increases accordingly, and the parasitic capacitance between the junction and the channel blocking region increases accordingly. This affects the circuit operation speed and increases the power consumption of the circuit.

In SOI circuits, the parasitic capacitance between the junction and the substrate is the buried insulator capacitance. This capacitance is proportional to the dielectric constant of the insulating layer Sio2, which is only 1/3 of Si. Moreover, as the size of the device decreases, the thickness of the buried Sio2 layer does not need to be reduced proportionally, and the parasitic capacitance will not increase. In addition, other parasitic capacitances of SOI devices, such as the silicon substrate and polysilicon layer, and the capacitance between metal interconnects are also reduced. As VLSI develops towards deep submicron, the reduction of parasitic capacitance will significantly increase the speed of the circuit.

2.2 Latching effect

The latch-up effect, also known as the thyristor effect, is a unique problem in bulk silicon CMOS circuits. From the CMOS cross-sectional structure diagram shown in Figure 2, we can see that there are two parasitic bipolar transistors, a vertical NPN and a horizontal PNP, which are composed of a substrate, a well, and a source-drain structure. If the internal resistance of the highly doped region is ignored, then these parasitic transistors together with Rw and Rs form the positive feedback circuit shown in Figure 3. When the current amplification factor β1*β2>1 and the base-emitter of the two transistors are forward biased, the latch-up effect can be triggered.

Figure 2 Bulk silicon CMOS cross-sectional structure

Figure 3 Equivalent circuit

If the SOI structure is used, since there is no conductive path to the substrate, the vertical path of the latching effect is cut off, so SOI has good anti-latching properties.

2.3 Hot Carrier Effect

As the device integration increases and the size decreases, the doping concentration of the substrate increases, while the power supply voltage does not decrease proportionally. This causes the lateral and longitudinal electric fields in the channel to increase sharply, and the carriers become hot carriers under the acceleration of the electric field. Some of them are injected into the gate oxide layer, changing the distribution of permanent charges in the oxide layer interface. This causes a decrease in transconductance, a shift in threshold voltage, and a decrease in leakage current. When the number of injections is large, the presence of gate current can be detected.

High-energy electrons also generate electron-hole pairs through impact ionization. The holes generated in the bulk silicon device flow into the substrate to form substrate current. There is a certain relationship between the substrate current and the gate current, and the device lifetime is related to the number of hot electrons injected into the gate oxide layer. The device lifetime г defined by the hot carrier degeneration of the gate oxide layer is related to the impact ionization current. In a fully depleted SOI MOSFET, M can be obtained by integrating the impact ionization coefficient near the drain end, and is related to the drain voltage and the gate voltage. The device lifetime is related to the amplification factor. Relevant studies have found [1, 5, 6, 7] that the hot electron degeneration in the fully depleted SOI MOSFET is weaker than that in bulk silicon, and SOI has a longer lifetime and higher reliability.

2.4 Radiation Effect

In the space environment, integrated circuits are exposed to nuclear radiation. MOS devices are multi-substance devices with strong resistance to neutron radiation, but they are quite sensitive to single event events (SEU) and gamma radiation.

When an energy-carrying particle (such as an alpha particle or a heavy ion) is incident on a reverse-biased PN junction depletion region and the underlying bulk silicon region, silicon atoms are ionized along the particle trajectory, generating electron-hole pairs. The existence of this trajectory causes the PN junction depletion layer near it to collapse for a short time, and deforms the equipotential surface of the depletion layer electric field, which is called a "funnel" (see Figure 4). In a bulk silicon device, under the action of the electric field, electrons will be collected by the depletion layer, while holes move downward and generate substrate current. These electrons reverse the logic state at the circuit node, causing soft failure of the circuit. In SOI devices, since there is a buried oxide layer between the active region and the substrate, the charge generated in the substrate region will not be collected by the junction of the SOI device, and only the charge generated in the top film can be collected, so SOI devices have the ability to resist soft failures, and the probability of single-particle events is much smaller than that of bulk silicon devices.

Figure 4: Energetic particle injection into bulk silicon and SOI

3. SOI Manufacturing Method

There are many methods to form SOI, such as deep implantation of oxygen or nitrogen into the silicon substrate, laser (or electron beam, infrared, etc.) annealing recrystallization of polysilicon on silicon dioxide, heating recrystallization of graphite strips of polysilicon on silicon dioxide, porous silicon oxidation, lateral epitaxy of silicon, silicon wafer bonding and thinning, etc. In recent years, the most developed and mature technologies are SIMOX technology, silicon wafer bonding [5, 8], and smart cutting [6, 7]. These three technologies are likely to be widely used in VLSI.

3.1 SIMOX technology

SIMOX (Separation by Implanted Oxygen) is one of the most feasible manufacturing methods for SOI materials. Its main advantage is that the silicon film and buried layer (BOX) produced are uniform. This is because the oxygen ion implantation uses the wafer surface as the reference surface, and the top silicon film and buried layer Sio2 can be transformed conformally during annealing.

The basic SIMOX process includes:

(1) Oxygen ion implantation (dose is about 3×1017-2×1018)

(2) High temperature (1 350°C) thermal annealing for 1-4h.

(3) Wafer cleaning (removing surface particles and contamination)

The ion implantation process plays a decisive role in SIMOX technology, determining the wafer yield, cost, and primary quality parameters.

In terms of SIMOX technology progress, two other significant advances are the increasing perfection of in-situ monitoring technology and chip electrical parameter characterization technology. The latest research shows [9, 12] that using a lightly doped substrate, the BOX thickness can be reduced to 50nm without affecting the power consumption characteristics of the circuit and speed. Because the parasitic capacitance in the SOI substrate mainly comes from the depletion layer and is almost independent of the BOX thickness. Low injection energy and injection dose can reduce chip contamination. A thin BOX layer can reduce the short channel effect, improve heat dissipation, and increase resistance to total radiation dose. Therefore, a low-dose, thin buried oxide layer (150-200nm) has become the development trend of SIMOX SOI materials.

3.2 Bonded and Etch-back SOI

The main process of silicon wafer bonding is as follows (Figure 6):

Figure 6 Principle of silicon wafer bonding technology

(1) The two silicon wafers that have been thermally oxidized are treated to be hydrophilic and then overlapped. The hydroxyl groups adsorbed on the surface are attracted to each other by Van der Wall forces at room temperature, so that the two silicon wafers are bonded together. They are then annealed at an appropriate temperature to enhance the degree of interfacial bonding.

(2) Active silicon layer: One of the layers is thinned to 1 μm using mechanical grinding and (chemical) polishing, forming an SOI structure.

Silicon wafer bonding technology is relatively expensive. In addition to some technical issues that need to be resolved, a major challenge it faces is how to reduce costs by simplifying process steps and improving equipment output capabilities.

3.3 Smart---cut

Smart cutting technology combines the advantages of SIMOX and silicon wafer bonding, successfully solves the problem of thinning silicon film in bonding SOI, and can obtain a top silicon film with good uniformity, and the quality of the silicon film is close to that of bulk silicon. In addition, the peeled silicon wafer can be used as the substrate for the next bonding, which greatly reduces the cost. This technology is one of the most popular SOI preparation technologies at present.

The originality of smart cutting lies in that H+ is injected and bubbles are formed under heating, so that the wafer breaks at the injection depth, achieving the purpose of thinning. The chemical reaction formula involved is as follows:

At the interface Si-OH +Si-OH→Si-O-Si+H2O

Si+ H2O→Sio2+ H2

When heated Si-H +Si-H→Si-Si+ H2

Smart cutting mainly includes four steps

(1) Ion implantation into silicon wafer A. A dielectric layer such as SiO2 is grown on A. The typical implantation dose is 3.5×1016～1×1017

(2) Perform RCA cleaning on A and support sheet B, and then bond them at low temperature. B acts as a "heating plate".

(3) Two-step heat treatment: 1) 400-600 OC to peel off A at the peak of H atom distribution, where a thin layer of single crystal silicon and support sheet B form an SOI structure (called Unibond SOI sheet). 2) (1 100 OC in nitrogen atmosphere) to enhance the bonding strength and restore the injection damage of the top silicon film.

(4) Surface polishing. Make the roughness ≤ 0.15um.

4 Problems and Challenges of SOI Technology

SOI CMOS is fully dielectrically isolated, has no latch-up effect, has a small active area, small parasitic capacitance, small leakage current, and can work in various harsh environments. Therefore, SOI CMOS has superior performance and is widely used in radiation-resistant circuits, high-temperature resistant circuits, submicron and deep submicron VLSI, low-voltage and low-power circuits, and three-dimensional integrated circuits.

Although SOI technology has many advantages that bulk silicon cannot match, and people have successively produced SOI devices and circuits with good performance, SOI has not yet been liberated from the laboratory to achieve large-scale production. The lack of low-cost and high-quality SOI substrate materials and the low yield of SOI ICs are the main obstacles for SOI technology to become mainstream.

SOI is very strict in the selection of materials. The silicon used to make MOS tubes must be crystalline silicon, and the insulator (Sio2) used must not contain any impurities, otherwise it cannot prevent the loss of electrons, making SOI technology meaningless.
In addition, so far, people still do not have a clear understanding of the floating effect of SOI and the floating threshold voltage, memory effect, hysteresis effect caused by the floating effect on the actual circuit and how to overcome it.

In terms of manufacturing technology, the latest trend of SIMOX materials is low dose, which can reduce costs but the thickness of buried oxygen is limited to 80-100nm. In addition, the biggest problem facing SIMOX is the use of non-standard instruments and equipment and heat treatment processes above 1300OC. This makes it difficult to prepare large-area (>300mm) SIMOX materials. Bonding technology can obtain high-quality silicon films close to silicon, and can obtain larger buried oxygen thickness and silicon film thickness. However, the thinning of silicon films and high costs are obstacles to the development of this technology. Although intelligent cutting technology is relatively perfect, the current control process is still imperfect.

References
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About the author Cui Shuai (1978-), male, master's degree student, graduated from the Department of Physics of Hebei University. His current interests include SOI technology, radiation hardening, and device reliability.