With the advent of the chiplet revolution, will technology companies take advantage of the situation or collapse?

The advent of chiplets is seen as a sign that people are trying to enhance computer system performance, even though the traditional Moore's Law is coming to an end.

Supporters believe that the use of small chips will not only lead to more specialized systems, but also bring higher yields to the chip industry. More importantly, this may prompt a major shift in the fabless semiconductor industry, driving the industry's final products into small, specialized chips that will be combined with general-purpose processors and other chips.

Intel has a technology development group in Oregon, where Ramune Nagisetty serves as the group's chief engineer. She has been committed to helping the entire industry build a chiplet ecosystem. In March this year, Ramune Nagisetty accepted an exclusive interview with IEEE Spectrum.

In this article, Ramune Nagisetty answers the following questions:

1. Definition and Importance of Chiplet

2. Intel's EMIB and applications

3. Existing problems and industry standards

4. Outlook for the future

When talking about the definition of the concept of "chiplet" and its importance, Ramune Nagisetty said:

In practical terms, a "chiplet" is a chip that encapsulates an IP (intellectual property) subsystem. It is usually integrated through advanced packaging or used through standardized interfaces. As for why they have become so important, it is because our computing and work types are exploding, and there is no one-size-fits-all solution to deal with these problems. Fundamentally, heterogeneous integration of best-in-class technologies is a way to continue Moore's Law.

Nagisetty believes that heterogeneous technology does not have to be done with silicon, it can also apply other types of semiconductors, such as germanium or III-Vs. Of course, we will have more types of semiconductor technologies in the future. Although we only have small chips based on silicon at present, they can be applied in different technologies. They can also be tuned in different fields such as digital, analog, RF and memory technology to obtain better performance. In this regard, the real driving force is the integration of memory. High bandwidth memory (HBM) is essentially the first proof of heterogeneous silicon packaging integration, and memory is essentially the first type of heterogeneous integration.

So what is Intel's EMIB (Embedded Multi-die Interconnect Bridge) that connects chiplets, and how does it work? Nagisetty said:

We can think of it as a high-density bridge connecting two chips, which is probably the best way to understand EMIB. I think many people are familiar with the use of silicon interposers as advanced packaging substrates because of their tight interconnectivity and built-in silicon vias, which make high-bandwidth connections between chips possible.

EMIB (circled in the figure) uses high-density interconnects to connect chips within the same package

The connection bumps that connect the chip to the EMIB have a finer pitch than normal bumps (bottom left).

Leifeng.com Note: [Image source: IEEE Owner: Intel]

EMIB is essentially a very small silicon interposer with very high density interconnectivity. The so-called microbumps are small balls of solder that connect chips to chips, and their density is much higher than that of standard package substrates. EMIB is generally embedded in a standard package substrate. With EMIB, you can achieve the highest interconnect density where you need it, and then use a standard package substrate to complete the rest of the interconnection.

There are many benefits to doing this, one of which is cost savings, as the cost of silicon interposers is proportional to the area. In this case, we can locate high-density interconnects where they are most needed. In addition, using a standard packaging substrate instead of a silicon interposer also has benefits in terms of overall embedding loss (signal attenuation due to material properties).

Nagisetty explained Intel's purpose of using EMIB:

Intel has demonstrated several applications for chiplets, and while two of them are based on EMIB technology, they are very different.

The first is Kaby Lake-G, which is where we integrate AMD's Radeon GPU and HBM with our own CPU chip. We use EMIB to integrate the GPU and HBM. Then we integrate the GPU and CPU via PCI Express (a standard circuit board interface) inside the package.

What's really interesting about this product is that we used components from different vendors and common industry standard interfaces (HBM and PCI Express) to create a best-in-class product. In this case, we took a component (GPU and HBM) that could be put on a board separately and then integrated it into a package. PCI Express can be used to send signals over long distances, which is more like a typical circuit board. Putting it in a package is not an optimal solution, but it is fast enough.

In addition to Kaby Lake-G, the next thing Nagisetty discussed was the Stratix 10 FPGA:

The center of Stratix 10 is Intel's FPGA, surrounded by six small chips, four of which are high-speed transceiver chips and two are high-bandwidth memory chips, all of which are packaged together. This product integrates six technologies contributed by three manufacturers, further demonstrating the interoperability between different manufacturers.

Stratix 10 FPGA uses the industry standard die-to-die interface AIB, which is Intel's Advanced Interface Bus. It was created for this product and is kind of an industry standard for high-bandwidth, logic-to-logic interconnect within the package. So, HBM is the first standard for memory integration, and AIB is the first standard for logic integration.

Intel Stratix 10 is a prime example of using EMIB to connect small chips in a package

Leifeng.com Note: [Image source: IEEE Owner: Intel]

As the center of this ecosystem, the real greatness of the AIB interface and FPGA is the mix-and-match model that is possible. Currently, many companies and universities have also implemented DARPA's CHIPS (Common Heterogeneous Integration and IP Reuse Strategy) to use AIB to create small chips.

The third example Nagisetty wanted to talk about was Intel's Foveros, which she said:

This is our logic-on-logic die stacking, which we first talked about last December. At CES in January, we announced a related product, Lakefield. Although it is integrated with chiplets, it is not stacked horizontally, but vertically.

This type of integration allows for extremely high bandwidth between the two chips, but it is based on an internal proprietary interface, and the two chips have to be designed essentially in sync to manage issues like power delivery and heat dissipation.

As for logic-on-logic die stacking, it may take a long time for industry standards to emerge, because the dies are essentially co-designed. Memory stacking built on logic may be where the 3D stacking standard is born.

Nagisetty also stressed that when designing stacked chips, it is important to consider heat dissipation:

It is not difficult to imagine that stacking will exacerbate the problem of heat, so we need to carefully design the board to deal with the heat. We also need to consider the architecture of the entire system. The application implications of 3D stacking will affect architectural decisions, not only the physical architecture, but the entire CPU or GPU and system architecture.

Also, if we want to demonstrate any interoperability, we need to have interoperable material systems. There is a lot of work to do to achieve interoperability, but I think thermal is the biggest challenge, with power delivery and power management a close second.

In addition to the above issues, it is also very important to establish industry standards for testing.

Normally, we test with packaged parts. So we have to package the chiplets that work so that we don't accidentally package the chiplets that have problems and lose yield. So we have to come up with a perfect test strategy. And we also need strong support from suppliers for power and heat. That means we have to connect all the integrated chips to manage both power and heat.

In terms of electrical operability, the interface AIB we released last July is actually just a physical-level standard, that is, an electrical and physical interface. Therefore, we also need standards that run through the upper-layer protocols.

The last standard is the mechanical standard, which is obvious. In fact, the placement of microbumps and the paths between bumps need relevant industry standards to ensure interoperability.

To know if a small chip is working properly, it is usually necessary to perform thermal testing on the packaged part. Therefore, we must test the bare die chip before the chip is packaged. Testing the packaged part, or delivering power to the packaged part, is relatively simple, while testing on the bare die is more challenging because the test requires additional design of the test probe.

Another thing is that everything that is needed to test the individual chiplets has to be designed into the chip, and the chiplets must be tested individually before packaging, which is very important, because if there are bad ones in the packaged chip, the good chips packaged together will be wasted.

This chip does give us a significant yield improvement, but that's one reason we use it, and not the only one. The key to improving yield is testing these chips before packaging.

This chip will also change the way things are designed , and high-bandwidth memory integration is an example. Currently, high-bandwidth memory is widely used in GPUs and high-performance AI processors. It seems that chiplets and memory integration have changed the way chips are designed and integrated.

The co-design of chiplets is definitely an important area of ​​development. I think there will be a lot of vendors offering these chiplets in the future. Understanding the needs of different chip vendors and communicating across boundaries is very important.

The advent and use of small chips is just the beginning of a revolution, and a new industrial ecosystem will develop around this. It will change the way we design chips or packaged components and change the evolution of the semiconductor ecosystem.

Nagisetty is optimistic about this new ecosystem:

I think this is a very exciting time for fabless startups because they have the opportunity to create smaller IP subsystems that can be very valuable when integrated using chiplets.

One of the goals of the DARPA chip program is to support the reuse of intellectual property and reduce the total amount of non-recurring engineering costs in producing products. The emergence of chiplets allows fabless startups to focus on the IP parts they are very good at without having to worry about the rest.

The development of small chips not only helps fabless startups, but also plays an important role in the Electronics Resurgence Program funded by DARPA. Although the number of companies capable of developing high-end semiconductor technology has declined in the past few years and the innovation capabilities of small and medium-sized enterprises have also been affected, this is an excellent opportunity for fabless startups to take advantage of the trend.

An innovative platform will be born in this field. Many changes will start from here and many opportunities will also be hidden here.

There are a lot of things happening very quickly to foster the development of this new ecosystem based on accelerator and packaging integration. We can’t tell how long it will take for this revolution to happen, but I think it won’t take too long, probably in the next few years.

The products Intel is bringing to market today are cutting-edge examples of how we can create new products in the future. We have many integrated solutions, but we are just beginning to move in this direction. However, with these technologies, we do have the ability to make greater progress than those who come after us.

Leifeng.com Note: This article is compiled from IEEE [Cover image source: website name IEEE, owner: Intel]

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