Vitis AI 2.5 takes AI acceleration to the next level

The model library of Vitis AI 2.5 has added popular NLP and more CNN models, such as Bert-base, Vision Transformer, end-to-end OCR, and SuperPoint and HFNet models for SLAM scenarios. With AMD's acquisition of Xilinx, AMD has further acquired excellent software and hardware capabilities; today, Vitis AI 2.5 supports 38 basic models and optimized models of the ZenDNN library of deep neural networks based on AMD EPYC server processors . It is conceivable that more AMD CPU users will experience faster AI performance acceleration through Vitis AI.

In the previous version, Vitis AI 2.0, we added the "Full Graph Optimizer (WeGO)" feature for the first time and received positive feedback from the developer community. By integrating the Vitis AI stack with mainstream AI frameworks, WeGO provides a convenient solution for deploying AI models on the cloud Deep Learning Processing Unit (DPU). In Vitis 2.5, WeGO further supports the Pytorch and Tensorflow 2 frameworks. In addition, 19 new examples such as image classification, object detection, and segmentation have been added to help users deploy AI models more smoothly on data center platforms.

The excellent AI acceleration performance on the AMD Xilinx platform is inseparable from a series of powerful AI acceleration engines and easy-to-use software tools. Currently, we provide scalable deep learning processor units (DPUs) to major FPGAs, adaptive SoCs, Versal ACAPs, and Alveo™ data center accelerator cards .

With the release of Vitis AI 2.5, Versal DPU IP can support multiple compute unit modes (Multiple compute unit) on the Versal AI Core series VC1902 device, support Depthwise convolution and LeakyReLU operator combination, etc.; Zynq Ultrascale MPSoC DPU IP has added Pool and Depthwise convolution functions implemented by the arithmetic logic unit (ALU), HardSigmoid and HardSwish functions, Depthwise convolution combined with LeakyReLU operator combination, in addition, it also supports large kernel-size MaxPool, large kernel-size AveragePool and rectangular kernel-size AveragePool, as well as new functions such as 16-bit constant weights.

The data center DPU IP now supports larger kernel-size Depthwise convolution (from 1x1 to 8x8), AI Engine-based pooling, ElementWise addition and multiplication, and large kernel-size pooling to meet more cloud AI application development needs.

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