Playing with HDMI2.1 source testing [Specification interpretation]

Currently, the mainstream HDMI standards on the market are 1.4b and 2.0, which support maximum resolutions/refresh rates of 4K@30Hz and 4K@60Hz, respectively. With the increasing demand for higher resolutions and refresh rates, the HDMI Association launched HDMI 2.1 in November 2017, adding the FRL (Fixed Rate Link) mode to support 8K@60Hz and 4K@120Hz.

The specific changes of FRL are: 1) The independent clock signal of the HDMI interface is embedded in the data, and the clock is recovered by a clock recovery unit at the receiving end; 2) There are up to 4 channels for transmitting audio and video data, and each channel supports a maximum rate of 12Gpbs; 3) The encoding method is changed from 8b/10b to 16b/18b, which has higher encoding efficiency.

The physical form of the interface has not changed. The original TMDS Clock channel is redefined as FRL lane 3; TMDS Data 0/1/2 correspond to FRL lane 0/1/2 respectively, as shown in the following figure.

In FRL mode, there are only 3 lanes and 4 lanes working modes. In the 3 lanes working mode, only 3 Gbps and 6 Gbps rates are supported. In the unused Lane3, both the source and sink need to use differential 50Ω~150Ω terminations. In the 4 lanes working mode, four rates of 6/8/10/12 Gbps are supported.

The Source must first read the Sink's EDID (EDID is a storage space with an I2C address of 0xA0/0xA1 and a length of 256 bytes, containing information such as the resolution and maximum rate supported by the Sink), and output the resolution/rate supported by the Sink. The Source cannot output a resolution/rate that is not supported by the Sink's EDID.

For Sinks that support HDMI2.1, SCDC_Present must be set to 1 in the HF-VSDB corresponding byte of EDID. The Max_FRL_Rate setting range is 1 to 6. The number 0 means that FRL mode is not supported. Other values ​​are reserved. Set Sink version to 1 in SCDC.

The specific meanings of the Max_FRL_Rate values ​​are as follows: the number 1 means that only the 3Gbps rate in the 3 lanes mode is supported, and other rates and lane configurations are not supported; the number 3 means that the 3Gbps and 6Gbps rates in the 3 lanes mode are supported; the 4 lanes mode only supports the 6Gbps rate, and other rates are not supported. The meanings of other numbers are similar.

>>> Link Training is required when the Source and Sink supporting FRL mode establish a connection for the first time. Link Training is also required to update the FRL rate.

The first training will go through 4 link training states in sequence:

Source TX tests are all completed in the LTS:3 state. The test equipment sets SCDC FLT_no_timeout to 1, so that the source will not exit the FRL LT state when it exceeds LT Tflt = 200ms. The test items require pattern and FFE level to be requested and issued in this state.

When Link updates FRL rate, the state LTS:4 Update FRL_Rate is used; when Link training fails or times out, the state LTS:L Legacy TMDS is entered. Source and Sink work in TMDS mode, which is HDMI1.4b/2.0 mode. The Link training state transition can also be seen in the figure below.

Since the FRL mode supports a maximum rate of 12Gbps, the oscilloscope bandwidth is required to be no less than 23G. There are two configuration methods to meet different customer needs; in addition, an HDMI2.1 fixture is required, and the EDID/SCDC controller also needs to support HDMI2.1 to achieve automated testing.

Configuration 1: Using SMA cable method

Two DPO 70000 SX oscilloscopes are synchronized using UltraSync cable, which can adjust the skew of all channels to within 1ps, ensuring the synchronization of all single-ended signal acquisition. The connection between the fixture and the oscilloscope uses SMA cable, which supports the simultaneous acquisition of 4 lane FRL signals. The test process does not require changing the hardware connection, the signal path is not attenuated, and the test speed is fast.

Configuration 2: Using Tri-mode probe P76/77xx

P76/77xx probes can be connected to the fixture with an SMA adapter.

Using the characteristics of the Tri-mode probe, the oscilloscope automatically controls the probe to work in single-ended mode A-GND and B-GND, completing the acquisition of the 4-lane FRL signal in multiple times. The test process does not require changing the hardware connection. The connection diagram is as follows. The oscilloscope will automatically de-embed the probe to eliminate the influence of the probe on the signal.

The FRL mode test software is Tekexpress FRL, and the software interface is as follows. According to the technical specifications of the product to be tested, select the minimum and maximum supported rates. Select the lane to be tested in Multi-lane setup. Select the corresponding test items in the Test Selection interface. The test items no longer distinguish between single-ended and differential, because the test solution can automatically realize the acquisition of all single-ended signals and the operation of differential signals.

Regardless of the configuration used, the FRL signal can be quickly verified using Tektronix automated test solutions.