Engineers say | RZ/V2H MPU improves AI performance and real-time control in robotics and autonomous applications
Today’s visual AI models face dynamic and complex environments, so improving energy efficiency and speed is a must for real-time applications.
To meet market demand, Renesas Electronics has launched a new generation of DRP-AI accelerators. The DRP-AI accelerator has an energy efficiency of up to 10 TOPS/W, 10 times higher than traditional technologies. It can not only run complex image AI models that previously required GPUs, but also consumes power as low as traditional embedded MPUs.
In addition to this AI accelerator, the high-end RZ/V2H microprocessor (MPU) is also equipped with an image processing accelerator using a dynamically configurable processor (DRP) , a quad-core Linux processor Arm ® Cortex ® -A55 running at up to 1.8 GHz, a dual-core 800MHz Arm Cortex-R8 high-speed real-time processor, and a sub-core Arm Cortex-M33 for I/O processing, using a heterogeneous multi-processor configuration.
The combination of 7 Arm-based CPU cores, the new generation DRP-AI and DRP can immediately process image recognition and AI judgment results in mechanical control, making it an ideal AI processor for the next generation of autonomous robots, autonomous mobile robots, drones and other applications. Read this article to learn more about the features of this new product.
For more information about the Dynamically Reconfigurable Processor (DRP), please copy the following link and open it in your browser:
https://www.renesas.cn/cn/zh/key-technologies/artificial-intelligence/drp
Next-generation AI accelerator DRP-AI
Renesas Electronics’ self-developed DRP-AI accelerator has been embedded in RZ/V2M, RZ/V2L and RZ/V2MA. At the same time, Renesas Electronics will also upgrade its original AI processor DRP-AI to a new generation to meet new market demands.
To significantly improve power efficiency, DRP-AI uses INT8 quantization technology and hardware support for unstructured pruning, which is difficult to achieve with traditional AI accelerators, thereby achieving up to 80 TOPS inference performance and 10 TOPS/W power efficiency. Read the white paper to learn more about unstructured pruning.
Copy the link below and open it in your browser to view Next-generation energy-efficient AI accelerator (DRP-AI3) white paper:
https://www.renesas.cn/cn/zh/document/whp/next-generation-highly-power-efficient-ai-accelerator-drp-ai3-10x-faster-embedded-processing
Figure 1 below shows a comparison of AI inference performance between different RZ/V products. For a common CNN type, Resnet50, its performance is 14 times higher than RZ/V2L when not pruned (dense model), and 45 times higher after pruning.
Figure 1 RZ/V series AI inference performance (excluding pre-/post-processing)
Dynamically configurable processor DRP helps OpenCV accelerator
Long before deep learning was invented, various methods were used for image recognition and decision making applications. One example is the open source computer vision library OpenCV. Even today, when AI image processing has become a reality, OpenCV is still a very useful technology. Today, visual AI and OpenCV can be used together in the right circumstances.
To accelerate AI and various image processing algorithms (such as OpenCV), the RZ/V2H MPU is designed with a dynamically configurable processor separate from the DRP-AI to provide the DRP library for the OpenCV accelerator and give full play to its flexible advantages.
Figure 2 below compares the performance of the OpenCV accelerator with DRP to the RZ/V2H quad-core CPU. For example, the Sobel filter for image edge detection is accelerated by 16 times, from 7.6 fps to 123 fps, using DRP acceleration.
Figure 2 OpenCV accelerator performance benchmark comparison
AI heterogeneous configuration + high-speed real-time control
Although high-speed multi-core Linux processors are ideal for image AI, they require large memory resources and have difficulty achieving the sub-millisecond real-time performance required for mechanical control.
To address this, the RZ/V2H uses a quad-core Cortex-A55 to run Linux programs (including AI processing), and a dedicated high-speed real-time processor for RTOS processing for applications that require high-speed real-time performance (such as motor control).
With OpenAMP, after connecting these different operating systems through inter-processor communication, the decision results of the DRP-AI and Linux processors can be reflected in the machine control in real time by the RTOS processor.
Figure 3 RZ/V2H block diagram
The RZ/V2H embedded AI microprocessor with these unique features is now in mass production, and the RZ/V2H evaluation board is ready to help you start your next vision AI development project.
You can click on the end of the article to read the original article to learn more about the RZ/V2H MPU. Visit the link below to explore the visual inspection single board computer that can be implemented as a system module (SOM) for development scalability or as an application-driven single board computer (SBC) solution .
Copy the link below and open it in your browser to view Visual inspection single board computer solution:
https://www.renesas.cn/cn/en/applications/industrial/building-automation/visual-detection-single-board-computer
The Renesas Engineering Community has many rich technical resources. If you have any questions when using Renesas products, you can scan the QR code below or copy the URL to open it in your browser to enter the Renesas Engineering Community to find answers and obtain online technical support.
https://community-ja.renesas.com/en/forums-groups/
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