Maxim Technology Focus | Higher Throughput, Lower Cost Semiconductor Test Solutions
By Robert Gee, Executive Business Manager, Core Products Division, Maxim Integrated
When semiconductor manufacturers evaluate new ATE systems for their fabs, they require higher density (i.e., more channels) for each generation of products in the same package size to maximize the use of their existing factory space. More channels can test more complex products or test the same products at a higher capacity.
Under this trend, almost all ATE designers are trying to increase the number of channels in each generation of products. Increasing test capabilities means that the main board (a driver board that integrates a large number of pin drive electronic devices) needs to work at very high power. Of course, from the perspective of long-term performance and reliability, it is very important to ensure a low operating temperature of the equipment. This means that the system needs high efficiency, high performance and compact underlying technology solutions.
Improving throughput is one of the best ways to reduce wafer test costs
Designers creating new ATE systems can effectively increase the number of channels by placing ICs more densely on the same size board. This approach results in increased heat dissipation, which can be addressed by using air-cooled or liquid-cooled heat sinks. However, liquid cooling is a very complex solution that requires a high level of expertise.
Alternatively, designers can consider the pin electronics inside the device more closely. An IC with a higher level of integration can effectively provide the required functionality without increasing the bill of materials (BOM) or the size of a discrete solution. In addition, the process structure of the IC needs to be considered. The candidate IC may support multi-channel applications, but can its own manufacturing process meet the efficiency and size requirements required by the design?
Maxim has a wafer manufacturing process customized for ATE architecture, and the MAX9979 dual-channel, 1.1Gbps pin electronics are manufactured using this process. As a monolithic IC, the MAX9979 is ideal for memory and system-on-chip (SoC) test applications and provides the following features:
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Driver/Comparator/Active Load (DCL)
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Integrated parametric measurement unit (PMU) per channel
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Built-in 16-bit level-setting digital-to-analog converter (DAC)
每路通道包括四电平引脚驱动器、窗口比较器、差分比较器、动态箝位、通用PMU、有源负载、高压可编程电平和14个独立的电平设置DAC。
器件采用黄金连接工艺设计 —— 这不是一般标准,而是支持更高功率密度的标准。
其双极晶体管设计旨在提供对称开关特性,因此上升和下降时间非常一致,所以信号发送至被测设备时,信号质量在系统中是尽可能保持均匀的。
Another performance advantage is the IC’s cable attenuation compensation feature. This feature allows designers to fine-tune each channel to optimize the waveform for the device under test (DUT). When there are multiple channels on a board, not all channels have the same length of traces or coaxial cable to the DUT. Cable attenuation compensation uses dual time constants to change the waveform so it is as symmetrical as possible when it reaches the DUT. The ability to calibrate both the drive signal to the DUT and the same signal on the return path of each channel ensures cleaner signal quality. Without the ability to correct or adjust the waveform, the choice of coaxial cable used in ATE designs becomes more critical, as each test head may use hundreds of the same cable. Waveform correction can reduce the distortion caused by lower quality, cheaper cables. Without this feature, the main way to achieve a high-quality signal is to use higher quality and more expensive coaxial cable.
The MAX9979 evaluation kit (EV kit) is a fully assembled and tested PCB that evaluates the MAX9979 dual-channel PEIC with PMU. The EV kit includes SMA connectors for high-speed digital I/O and MAX9979 pin-driver outputs. The MAX9979 EV kit connects to a computer through a universal serial bus (USB) port. The EV kit also includes Windows® 2000/XP- and Windows Vista®-compatible software that provides a simple graphical user interface (GUI) for exercising the performance of the MAX9979.
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