HHGrace's unique technology path

Source: The content comes from "Guojun Electronics Wang Cong Team", thank you.

On March 21, SEMICON China invited Dr. Kong Weiran, Executive Vice President of Shanghai Huahong Grace Semiconductor Manufacturing Co., Ltd., to give a speech on "Using Innovation to Promote Development - Huahong Grace's Characteristic Process Path". Dr. Kong gave a detailed discussion on Moore's Law, Huahong Grace's characteristic process and technical route.

The following is the full text of the minutes (recorded for investors' reference only, please refer to the company's press release for details):

The speech is mainly divided into three parts: 1. Moore's Law and special processes; 2. Hua Hong Hong Li's special processes (Flash+high voltage); 3. Hua Hong Hong Li's 8+12 technology route

1. Moore's Law and Special Processes

The number of MOS transistors on CPU chips continues to increase, in line with Moore's Law. As the size of transistors continues to scale, the operating voltage of the CPU core continues to decrease. However, after the 13th process, the voltage reduction stagnated until the emergence of new technologies such as FinFet, which allowed it to continue to decrease. After the voltage is no longer reduced, the application-side chips gradually distance themselves from each other. The company's 8-inch technology tends to be biased towards devices such as analog with higher voltages, while the logic integration is very high, and the logic operation has been advancing with the advanced process nodes. The emergence of advanced processes will eliminate old processes, but some practical applications do not require too advanced process technology, otherwise the converted chips will be too small to be packaged.

MOSFET is the core of the entire IC, but it lacks breakthrough innovation. Below is a cross-sectional view of a MOSFET. MOSFET is the core of the entire IC. DRAM, 3D NAND, Trench MOS, IGBT, FDSOI and FINFET all use MOS as the core device. Since the advent of MOS 60 years ago, the structural principle has not changed substantially. At present, the process evolution mainly relies on the reduction of the precision of the lithography machine, the use of high K gate oxide and FinFet and other technologies, and the semiconductor process still lacks breakthrough innovation.

Next, Dr. Kong introduced the company's special processes, including Logic/Analog, Smart Card and MCU in the digital and memory categories; BCD, RFCMOS and RF-SOI in the analog RF category; Power MOS, IGBT and Deep Trench Super-Junction in the discrete power category; MEMS in the sensor category, etc. All the special processes basically have high-voltage MOS (>6V). It is precisely because of this high voltage that the Flash scaling is slow.

Dr. Kong then introduced the application of Flash in embedded systems. The traditional mainstream includes Floating Gate 2T (can be NMOS or PMOS); SONOS 2T; SONOS 1.5T is mainly made by a well-known Japanese company, which stacks two transistors together to achieve 1.5T; Floating Gate SST Split Gate is divided into ESF1/2/3 generations; and finally the company's own invention, NORD Flash. In terms of new material storage, such as RRAM, PCRAM and MRAM, the company has not yet involved, but the company has been keeping an eye on it.

Below is a screenshot of a paper published by STM (STMicroelectronics) at the 2018 IEDM conference. They invented the vertical 1.5T eSTM technology, which achieved further size reduction.

2. Hua Hong Hongli's special process (Flash + high voltage)

The following is the company's unique technology patent, which is to transform three transistors into a floating gate. The circuit model is shown in the upper right corner of the figure, which includes a channel and three gates. The existing model does not support the new device structure, so it has to use the wrong structure in the lower right corner for numerical approximation simulation.

The company's innovative flash memory cell has a clear advantage in area. The flash cell size is ahead of NonSelfAligned and SelfAligned cells. At the 55nm node, the company's new flash memory cell size is only about 0.04um2.

While balancing the flash memory cell area and performance, the company focused on Flash_2 cell, published this work in IEEE, and applied for related patents.

The figure below shows that under a single 1.5V power supply, the smaller the flash cell, the smaller the IP core area. The reduction is more obvious in 512KB, and the Flash IP area is continuously optimized.

Another innovative work of the company is to continuously reduce manufacturing costs. The company has gradually reduced the number of mask layers from 38 in 2007 to 24 in 2018 (1.5V+5V+Flash), reaching the industry-leading level. At the same time, the company realizes that the mask layer has not reached its limit. In the future, the company will launch the ultimate mask layer to continuously reduce manufacturing costs.

In summary, the company's E-Flash technology development strategy includes the following five points: (1) Device scaling: using self-aligned process to reduce dependence on advanced lithography; (2) Data Retention: maintaining 90A oxide (can withstand 300°C high temperature baking); (3) Endurance: not dependent on ECC; (4) continuing to simplify the process and simplify the number of lithography layers; (5) continuing to look for new device structures.

One of the company's best-selling products in high-voltage devices is Super Junction MOSFET . However, high-voltage drain relies on epitaxial, and the dielectric layer formed after the N-Type and P-Type are fully depleted is resistant to high voltage. In order to achieve precise control, the industry usually uses multi-epitaxial, which has good performance but high cost. The company directly etches, and the product profile is very beautiful, and the arrangement will become tighter and tighter. When the on-resistance is halved, the die size will also be reduced by 1 time, and the cost will be reduced. The on-resistance of the company's products is only 0.7 square ohms, setting a new record.

The company’s latest breakthrough is 7V Analog. The cumulative shipments of the 0.35-micron 5V/7V analog platform are 500,000 pieces, and the company is also continuously improving its stability.

Competition in BCD technology is fierce. Currently, the company has developed to 90nm, keeping up with the advanced level of the industry. The company will also push this to 12-inch wafer manufacturing.

The company's latest generation of RF-SOI is also at a high level in the industry, and will follow market trends to integrate RF-Switch and LNA. With the continuous advancement of technology, it may even be possible to integrate PA in the future.

Through years of practice, the company has vigorously developed differentiated technologies and continued to innovate, with revenue growing continuously. In 2018, total revenue was close to US$1 billion.

The company's development is inseparable from the support of R&D. By 2018, the company had more than 3,000 authorized patents.

The figure below is the "8+12" technology roadmap. The company has a complete characteristic process platform, based on which it will continue to extend to 12 inches to solve the capacity problem and provide a broader space for technology development. In the future, more competitive differentiated technologies will be launched. Dr. Kong finally emphasized that the current 8-inch wafer still has a large market demand and development space.

*The content of the article represents the author’s personal opinion and does not represent Semiconductor Industry Observer’s agreement or support for that opinion.

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