Introduction to chip production and packaging technology

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Chips are the most critical components of electronic products, so what is the chip production and packaging process like? This article compiles some videos and abstracts from the Internet, hoping to be helpful to friends who are willing to learn about chip production and packaging knowledge!

1. Chip production: Please watch the following video to understand the wafer manufacturing process:

2. IC packaging knowledge <fieldset style="margin: 0px; padding: 5px; max-width: 100%; min-width: 0px; color: rgb(62, 62, 62); white-space: normal; border: 1px solid rgb(204, 204, 204); text-align: justify; background-color: rgb(250, 250, 240); font-family: 微软雅黑; font-size: 14px; box-shadow: rgb(165, 165, 165) 5px 5px 2px; box-sizing: border-box ; word-wrap: break-word ;"> <legend style="margin: 0px; padding: 0px; max-width: 100%; text-align: center; box-sizing: border-box ; word-wrap: break-word ;"> <p style="margin-top: 0px; margin-bottom: 0px; padding: 4px 10px; max-width: 100%; min-height: 1.5em; white-space: pre-wrap; line-height: 2em; background-color: rgb(0, 112, 192); color: rgb(255, 255, 255); box-shadow: rgb(165, 165, 165) 4px 4px 2px; border-top-left-radius: 2em 0.5em; border-top-right-radius: 1em 3em; border-bottom-left-radius: 1em 3em; border-bottom-right-radius: 4em 0.5em; box-sizing: border-box ; word-wrap: break-word ;"> concept </legend> Packaging refers to connecting the circuit pins on the silicon chip to the external connector with wires so as to connect with other devices. The packaging form refers to the shell used to install the semiconductor integrated circuit chip. It not only plays the role of installing, fixing, sealing, protecting the chip and enhancing the electrical and thermal performance, but also connects the contacts on the chip to the pins of the package shell with wires. These pins are connected to other devices through wires on the printed circuit board, thereby realizing the connection between the internal chip and the external circuit. </fieldset> Because the chip must be isolated from the outside world to prevent impurities in the air from corroding the chip circuit and causing electrical performance degradation. On the other hand, the packaged chip is also easier to install and transport. The quality of packaging technology also directly affects the performance of the chip itself and the design and manufacture of the PCB (printed circuit board) connected to it, so it is crucial. An important indicator for measuring the advancement of chip packaging technology is the ratio of chip area to packaging area. The closer this ratio is to 1, the better. The main factors to consider when packaging: 1. The ratio of chip area to package area should be as close to 1:1 as possible to improve packaging efficiency; 2. The pins should be as short as possible to reduce delay, and the distance between pins should be as far as possible to ensure no interference and improve performance; 3. Based on the heat dissipation requirements, the thinner the package, the better. The packaging is mainly divided into two types: DIP dual in-line package and SMD chip package. In terms of structure, the packaging has experienced the earliest transistor TO (such as TO-89, TO92) package development to dual in-line package, and then PHILIP developed the SOP small outline package, and then gradually derived SOJ (J-type pin small outline package), TSOP (thin small outline package), VSOP (very small outline package), SSOP (shrink SOP), TSSOP (thin shrink SOP) and SOT (small outline transistor), SOIC (small outline integrated circuit), etc. In terms of material medium, including metal, ceramic, plastic, plastic, many circuits with high-intensity working conditions such as military and aerospace levels still have a large number of metal packages. Packaging has roughly gone through the following development process: In terms of structure: TO->DIP->PLCC->QFP->BGA->CSP; Materials: metal, ceramics -> ceramics, plastics -> plastics; Pin shape: long lead straight insertion-> short lead or leadless mounting-> ball bump; Assembly method: through-hole mounting->surface mounting->direct mounting Specific packaging form 1. SOP/SOIC package SOP is the abbreviation of Small Outline Package. SOP packaging technology was successfully developed by Philips in 1968-1969, and later gradually derived SOJ (J-type pin small outline package), TSOP (thin small outline package), VSOP (very small outline package), SSOP (shrink SOP), TSSOP (thin shrink SOP) and SOT (small outline transistor), SOIC (small outline integrated circuit), etc. 2. DIP package DIP is the abbreviation of Double In-line Package. It is a plug-in package with pins extending from both sides of the package. The packaging materials are plastic and ceramic. DIP is the most popular plug-in package, and its application range includes standard logic IC, memory LSI, microcomputer circuit, etc. 3. PLCC package PLCC is the abbreviation of Plastic Leaded Chip Carrier, which is a plastic J-lead chip package. PLCC packaging is square in shape, 32-pin package, with pins all around, and its size is much smaller than DIP package. PLCC package is suitable for installation and wiring on PCB using SMT surface mounting technology, and has the advantages of small size and high reliability. 4. TQFP package TQFP is the abbreviation of thin quad flat package. The quad flat package (TQFP) process can effectively utilize space, thereby reducing the space requirements for printed circuit boards. Due to the reduced height and volume, this packaging process is very suitable for applications with high space requirements, such as PCMCIA cards and network devices. Almost all ALTERA CPLD/FPGAs have TQFP packages. 5. PQFP package PQFP is the abbreviation of Plastic Quad Flat Package. The distance between the chip pins in PQFP is very small, and the pins are very thin. Generally, large-scale or ultra-large-scale integrated circuits use this packaging form, and the number of pins is generally more than 100. 6. TSOP package TSOP is the abbreviation of Thin Small Outline Package. A typical feature of TSOP memory packaging technology is that pins are made around the packaged chip. TSOP is suitable for installation and wiring on PCB (printed circuit board) using SMT technology (surface mounting technology). When the TSOP package size is small, the parasitic parameters (when the current changes greatly, it causes output voltage disturbance) are reduced, which is suitable for high-frequency applications, easy to operate, and has high reliability. 7. BGA package BGA is the abbreviation of Ball Grid Array Package. In the 1990s, with the advancement of technology, the integration of chips continued to increase, the number of I/O pins increased dramatically, power consumption also increased, and the requirements for integrated circuit packaging became more stringent. In order to meet the needs of development, BGA packaging began to be used in production. Memory packaged with BGA technology can increase the memory capacity by two to three times without changing the volume. Compared with TSOP, BGA has a smaller volume, better heat dissipation and electrical performance. BGA packaging technology has greatly increased the storage capacity per square inch. The volume of memory products using BGA packaging technology is only one-third of that of TSOP packaging at the same capacity. In addition, compared with the traditional TSOP packaging method, BGA packaging has a faster and more effective heat dissipation path. The I/O terminals of the BGA package are distributed under the package in an array form with circular or columnar solder joints. The advantage of BGA technology is that although the number of I/O pins has increased, the pin spacing has not decreased but increased, thereby improving the assembly yield rate; although its power consumption has increased, BGA can be welded using the controlled collapse chip method, thereby improving its electrothermal performance; the thickness and weight are reduced compared to previous packaging technologies; parasitic parameters are reduced, signal transmission delay is small, and the frequency of use is greatly improved; coplanar welding can be used for assembly, and the reliability is high. When talking about BGA packaging, we have to mention Kingmax's patented TinyBGA technology. TinyBGA is called Tiny Ball Grid Array in English, which is a branch of BGA packaging technology. It was successfully developed by Kingmax in August 1998. The ratio of its chip area to package area is not less than 1:1.14, which can increase the memory capacity by 2 to 3 times without changing the volume. Compared with TSOP packaging products, it has a smaller volume, better heat dissipation performance and electrical performance. Memory products using TinyBGA packaging technology have a volume of only 1/3 of that of TSOP packaging with the same capacity. The pins of TSOP packaged memory are led out from the four sides of the chip, while TinyBGA leads out from the center of the chip. This method effectively shortens the signal transmission distance, and the length of the signal transmission line is only 1/4 of the traditional TSOP technology, so the signal attenuation is also reduced. This not only greatly improves the chip's anti-interference and anti-noise performance, but also improves the electrical performance. Chips packaged with TinyBGA can withstand up to 300MHz external frequency, while traditional TSOP packaging technology can only withstand up to 150MHz external frequency. The memory packaged in TinyBGA is also thinner (package height is less than 0.8mm), and the effective heat dissipation path from the metal substrate to the heat sink is only 0.36mm. Therefore, TinyBGA memory has higher thermal conductivity efficiency, is very suitable for systems that run for a long time, and has excellent stability. Information on the packaging naming rules of some international brand products 1. MAXIM For more information, please refer to www.maxim-ic.com MAXIM starts with "MAX". DALLAS starts with "DS". MAX××× or MAX×××× illustrate: 1. Suffix CSA, CWA, where C stands for standard grade, S stands for surface mount, and W stands for wide body surface mount. 2. The suffix CWI indicates wide-body surface mount, EEWI indicates wide-body industrial-grade surface mount, and the suffix MJA or 883 indicates military grade. 3. The suffixes of CPA, BCPI, BCPP, CPP, CCPP, CPE, CPD, and ACPA are all ordinary dual in-line plug-ins. Example MAX202CPE, CPE ordinary ECPE ordinary with antistatic protection MAX202EEPE Industrial grade antistatic protection (-45℃-85℃), E refers to antistatic protection MAXIM digital arrangement classification 1-digit simulator; 2-digit filter; 3-digit multi-way switch; 4-digit amplifier; 5-digit digital-to-analog converter; 6-digit voltage reference; 7-digit voltage conversion; 8-head resetter; 9-digit comparator; DALLAS naming convention For example, DS1210N.S. DS1225Y-100IND N=industrial grade S=surface mount wide body MCG=DIP seal Z=surface mount wide body MNG=DIP industrial grade; IND=industrial grade QCG=PLCC package Q=QFP; 2. For more information about ADI, please visit www.analog.com AD products mostly start with "AD" or "ADV", but some also start with "OP" or "REF", "AMP", "SMP", "SSM", "TMP", "TMS", etc. Description of suffix: 1. The suffix "J" indicates a civilian product (0-70℃), "N" indicates ordinary plastic sealing, and the suffix "R" indicates surface mount. 2. The suffix D or Q indicates ceramic seal, industrial grade (45℃-85℃). The suffix H indicates round cap. 3. The suffixes SD or 883 are military products. For example: JN DIP package JR surface mount JD DIP ceramic package 3. BB For more information, please visit www.ti.com BB product naming rules: The prefix ADS is for analog devices. The suffix U is for surface mount. P is for DIP package. The prefix B indicates industrial grade. The prefixes INA, XTR, PGA, etc. indicate high-precision op amps. The suffix U is for surface mount. P stands for DIP. PA stands for high precision. 4. INTEL For more information, please visit www.intel.com INTEL product naming rules: The N80C196 series are all single-chip microcomputers; Prefix: N=PLCC package T=industrial grade S=TQFP package P=DIP package; KC20 main frequency KB main frequency MC represents 84 leads; For example: TE28F640J3A-120 flash memory TE=TSOP DA=SSOP E=TSOP. 5. For more information about ISSI, please visit www.issi.com Beginning with "IS" For example: IS61C IS61LV 4× indicates DRAM 6× indicates SRAM 9× indicates EEPROM; Package: PL=PLCC PQ=PQFP T=TSOP TQ=TQFP; 6. LINEAR For more information, please visit www.linear-tech.com Prefix with product name LTC1051CS CS means surface mount; LTC1051CN8 ** indicates *IP package 8 pins; The suffix C stands for civilian grade and I stands for industrial grade, and the following numbers indicate the number of pins! 7. For more information about IDT, please visit www.idt.com IDT's products usually start with IDT Description of suffix: 1. The suffix TP belongs to narrow body DIP 2. The suffix P is for wide-body DIP 3. The suffix J is PLCC For example: IDT7134SA55P is a DIP package IDT7132SA55J is a PLCC IDT7206L25TP is a DIP 8. NS For more information, please visit www.national.com NS products start with LM or LF LM324N 3 prefix represents civilian products with N round cap; LM224N 2 prefix represents industrial grade with N plastic seal; LM124J 1 prefix represents military products with J ceramic seal; 9. HYNIX For more information, please visit www.hynix.com Package: DP stands for DIP package, DG stands for SOP package, DT stands for TSOP package. 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Introduction to chip production and packaging technology