In those years, we pursued Moore's Law together

(one)

These are vivid stories that

tell you how Moore's Law affects your life.


If you only know one story about integrated circuits,

it should be Moore's Law - the feature size of semiconductor processes is halved every 18 months. Like mathematical laws, Moore's Law has many inferences, such as that in the same cycle (i) the production cost of chips with the same number of transistors (ii) the power consumption of chips with the same performance (iii) the delay of logic gates with feature sizes ... all decrease exponentially. What circuits best reflect Moore's Law? Processor chips, CPU/GPU, etc. After all, Mr. Moore is the boss of Intel. For example, the mobile phone processing chip in everyone's hand has performance equivalent to the supercomputer Cray-2 30 years ago , but the power consumption is only one hundred thousandth of that of Cray-2. So, the question is, which inference should the development of processor design be based on? Cheaper? Lower power consumption? Faster? Before 2005, all designs were striving for faster speeds. This is the CPU frequency we have heard of. It took less than 30 years to increase from 6MHz of 80286 to 3.6Ghz of Pentium IV, which is 600 times. If it had developed at this rate from 2005 to now, wouldn’t the current CPU have run at more than 20GHz ? However, the story did not go on happily as the script said. Today’s CPU frequency is only 5GHz



























































because it encountered two big demons - heat dissipation and data access . First of all, heat dissipation. In fact, there is another inference of the classic Moore’s Law. In the same cycle, the heat generation per unit area also increases exponentially. After all, you can’t ask a horse to run fast and not eat grass. ****Evil voice-over**** Later, everyone felt that this inference was too bad, so it was put into the cold palace. ***End of voice-over*** Anyway, soon heat dissipation became an important factor limiting the frequency increase of processors used in personal computers . After all, adding water cooling and liquid nitrogen to a PC is too weird.






































However, the data access problem is more serious.

We have an old saying:

A good cook cannot cook without rice.

In the PC scenario,

the CPU is the good cook.

The source data to be calculated is rice.

Even if the CPU's main frequency reaches 10GHz

, it means that the CPU can only perform 10 to the 10th power operations per second.

Then there must be other chips to feed the "rice" .


And data of a slightly larger scale exists in

memory chips/Flash chips/SSD chips/hard disks

. In short, it is not in the CPU chip.

Therefore, when the CPU starts a new round of calculations,

it has to ask other chips in the cloud for data.

However, their reading and writing speeds are slow.

One time is about 100 times the processor clock cycle.

At this time, the CPU can only wait for 100 cycles

. The professional term is called stall.

Therefore, the faster the CPU's main frequency,

the more it highlights the "pig teammate" attribute of the memory chip.



So in the past decade,

the development script of the processor has become

a medium frequency + multi-core configuration

, just like summoning a super awesome big devil

to summoning a combination of multiple heroes.


On the other hand, more and more silicon engineers

have begun to study memory chips that increase access speed.

The main focus is on two indicators:

one is access delay, and the other is bandwidth.

These two concepts can be explained by couriers.

Delay is the time it takes for the courier to arrive downstairs at your house.

Bandwidth is how many goods a courier can deliver at a time.


For the classic memory solution, DRAM,

due to its capacitor storage principle and refresh mechanism,

DRAM has an inherent defect of large access delay,

so more efforts are put into increasing bandwidth.


In fact, with the emergence of multi-core,

high-bandwidth memory access can modify the defect of access delay .

In the single-core era, if you place n orders, the courier will deliver n times. In the

multi-core era, if you place n orders, the awesome SF Express courier may deliver them all in one truck.

In this way, the time you wait is still shortened

. Therefore, high bandwidth is particularly meaningful.



In fact, where is the actual bottleneck of access bandwidth?

It is mainly the line width of the printed circuit board (PCB).

The standard minimum line width of the PCB motherboard has been 3 mil (about 75 um) since ten years ago,

and it is still 3 mil today, with almost no progress!

(Do you suddenly feel that Moore's Law is awesome?!)

Therefore, this fact of no progress also brings a lot of inferences.

The connection density between the processor and the memory remains unchanged.

The number of connections between the processor and the memory will not change significantly.

From DDR1 to DDR4, the bit width

has been 64bit for 15 years. Therefore, the access bandwidth has only increased by 12 times in 15 years.



The motherboard that does not change with Moore's Law


. So how to make the gap between memory and processor keep up with Moore's Law?

To know what happened next, please listen to the next analysis -

the dimensional revolution of advanced packaging technology

(two)

Continuing from what we said last time,
even though integrated circuits have developed rapidly along with Moore's Law,
due to the size limitations on PCBs,
the performance of processors we actually use
has not improved as much as Moore's Law.
This has hurt the glass hearts of Moore's fans.

So,
on a dark and windy night,
Moore's silicon engineers launched a dimensional revolution. Because when human civilization has evolved to a bottleneck, it is a common choice to find solutions from a higher dimension. Just like when ground roads cannot meet the travel needs of urban residents, subways and elevated roads came into being.

Traditional two-dimensional circuits
refer to chips soldered on the motherboard and
are interconnected in two
dimensions that is, there is only
one chip in the same position that realizes a certain function and
the interconnection between chips can only rely on the routing between PCB boards
so the number of layers and line width of PCB determine the storage access bandwidth

the so-called dimensionality revolution
is to stack multiple chips in the same position
for example
stacking processor chips and memory chips up and down
using routing in the package instead of PCB routing
to achieve the interconnection between the two
thus, using the high density of routing in the package
to increase data access bandwidth
while reducing routing length and
comprehensively improve data access latency

obviously, the core of this dimensionality revolution is
how to make the routing in the package keep up with Moore's Law?
At present, the most promising package routing is called TSV Through Silicon Via. The through-hole TSV between chips

directly upgrades the two-dimensional structure of chip interconnection to three-dimensional
through vertical routing, greatly improving the interconnection density per unit area. The bit width has also increased from the 64-bit fate of the DDR standard to 512-bit or even 1024-bit . So, the gunshot of the revolution sounded. Another great advantage of using TSV is that it can stack chips under different processes to create more possibilities for SoC. In the current integrated circuit manufacturing, there are different processes according to different functions . For example, the DRAM process requires a deep trench process to make large capacitors, and the RF process requires thick metal to make high-Q large inductors. The analog process requires high voltage and low layout effects for matching. These characteristics are actually ignored by the pure Moore's Law , and they are not necessarily compatible with the standard CMOS process. The one-sided pursuit of realizing all circuits on the same chip often does not make up for the gains. In addition to increasing the dimension, 3D TSV packaging also provides a platform that cleverly integrates all technologies. However, at this time, silicon workers heard a series of ancient terrible legends: In the dark forest of the vast universe, there is an extremely terrifying weapon, the two-dimensional foil , which can destroy all high-dimensional civilizations ...































(Please refer to "The Three-Body Problem")

Just as the two-dimensional foil is the ultimate challenge to human civilization,
high-dimensional 3D packaging also has many rough spots and
has a series of problems such as stability and reliability.

So the thought of going down a little bit appeared.
What is higher than two dimensions and lower than three dimensions? 2.5 Dimension! 2.5D packaging covers the chip on the same silicon substrate (interposer) and uses the wiring on the substrate to achieve interconnection. Since the substrate is made of silicon material, the achievable wiring line width meets the semiconductor process and is much smaller than the PCB board wiring . Therefore, the interface width can also be very high, so the skill meets the performance requirements of keeping up with Moore's Law and can improve stability and reliability. In addition, 2.5D has another advantage, which is cheap.













However, silicon engineers are always dissatisfied.
After all, for a slightly larger 2.5D package,
the substrate area is huge.
Since the substrate is also based on integrated circuit technology,
it is also a lot of money.

Therefore,
a 2.75D has emerged.
2.75 is just something I made up
. Anyway, it is between 2.5 and 3.
The scientific name is high-bandwidth memory package (HBM).
It is mainly led by mainstream GPU chip companies
(AMD & NVDIA).
3D packaging is used to stack multiple memory chips together.
Then 2.5D technology is used to interconnect the stacked memory chips and GPU on the substrate


. In this way, only the 3D packaging of chips of the same type needs to be optimized.
The complexity of the problem is not high,
but it can quickly improve the performance of GPUs that are restricted by memory bandwidth.

In
fact, GPUs do not simply do image processing.
Its large-scale parallel structure
is also an important tool for large-scale computing.
It is this feature of GPU
that makes deep machine learning possible
. The voice-over ends.

So,
if ds silicon
engineers ... Can I be rich enough to use a TSV?
Um... Well,
if you can afford 16nm FinFET,
of course you can.
The 2.5D/3D packaging process currently provided by TMSC includes
two high-dimensional packaging designs
(i) CoWoS (for rich users)
(ii) InFO-WLP (for DS users).
It is said that the iPhone 7 to be released soon uses InFO.

Of course, there is another way, which
is to open Cadence IC616
in Layout Editor. Okay,

that's it.
This is the first story in the Moore's Law series of this public account.

We are committed to telling you how many real changes have taken place in the semiconductor world
because of Moore's Law.
If you have any suggestions or opinions for us, please leave a message.

This article is reprinted with permission from Silicon Talks (WeChat ID: silicon_talks). The views expressed are the author’s personal and do not represent the views of this public account.

Previous Review:

Where is Moore's Law going? Part 1: Where did Moore's Law come from? Has Moore's Law reached its limit?

Where is Moore's Law Heading? Part 2: More Moore or More Than Moore?

Where is Moore's Law Heading? Part 3: Beyond CMOS