Foundry giants, new competition

What is foundry 2.0? In the past, the concept of foundry was usually equated with the manufacturing and processing of finished wafers. However, TSMC Chairman Wei Zhejia believes that the 2.0 version of foundry includes packaging, testing, mask production and other links, excluding the IDM (integrated device manufacturer) of memory chips.

To put it simply, except for chip design, everything else can be classified into foundry 2.0.

TSMC pointed out that the new definition can more fully reflect the expanding future market opportunities. According to the 2.0 definition, the scale of the wafer manufacturing industry will reach nearly US$250 billion in 2023, a significant increase compared to the US$115 billion defined in version 1.0. It is estimated that the wafer manufacturing industry will grow by nearly 10% year-on-year in 2024.

Data from research firm TrendForce shows that under the old definition of wafer foundry, TSMC's Q1 market share reached 61.7%, while using the new definition, TSMC's total market share of wafer foundry business in 2023 will be 28%.

TSMC CFO Huang Renzhao said that the reason for redefining wafer foundry is that the boundaries of wafer foundry are gradually blurring as international IDM manufacturers are entering the foundry market. On the other hand, TSMC also needs to continuously expand its foundry influence, especially in the field of advanced packaging.

However, TSMC also reiterated that it will focus on the most advanced back-end technology to help customers create forward-looking products. In other words, in the future it will still focus on advanced packaging rather than being involved in the entire packaging market.

As early as 2021, Intel proposed the IDM 2.0 strategy, separated its foundry department, and began to accept orders from other fabless companies. Now TSMC has proposed the concept of Foundry 2.0, which feels somewhat tit-for-tat. Although TSMC has received orders for Intel's new processors, the two manufacturers are already direct competitors in the foundry market.

Who is the real OEM 2.0?

In 2021, after Pat Gelsinger took over as Intel CEO, he announced a bold IDM 2.0 plan. He said that Intel's future goals included becoming a leading semiconductor foundry. At the time, this plan was somewhat unrealistic. The reason was that Intel not only lagged behind TSMC in process nodes, but even lost to Samsung.

Intel is well aware that the semiconductor process technology it once prided itself on is now inferior to others, and the backwardness of the technology has in turn affected its own processors. When the traditional PC and server processor markets face more intense competition, the former giant is in urgent need of a revolution.

The IDM 2.0 strategy is this revolution, and it includes three key components: 1) expanding Intel’s manufacturing capabilities to adopt industry-leading process technologies, 2) expanding the use of third-party foundry capabilities to meet Intel’s internal needs, and 3) becoming a world-class foundry with the goal of becoming the second largest foundry by 2030. To achieve these high goals, Intel has committed to delivering five new process nodes in four years to regain process technology leadership and plans to invest $100 billion to expand capacity by expanding existing factories and building six new factories in Arizona, Ohio, and Germany.

First of all, it is clear that the wafer fab may be the most expensive link in chip production. IDM and Foundry not only need to continuously invest in new manufacturing process technologies to continue to improve semiconductor performance, density and cost, but also need to continue to invest in new manufacturing capabilities. Historically, both expenses have grown exponentially. Intel estimates that the shift to extreme ultraviolet lithography (EUV) technology will increase the cost of new factories to approximately $25 billion, and the next-generation high numerical aperture (High-NA) EUV technology will further increase costs to $30 billion. Its high cost has actually excluded manufacturers other than Intel, TSMC and Samsung.

This is also one of the reasons why Intel turned to the foundry field. In terms of advanced processes, Intel actually has only two competitors. Both of these manufacturers are located in East Asia, which is a long geographical distance from North American chip design companies. As a local American manufacturer, Intel has inherent advantages.

However, this geographical advantage will not directly translate into an advantage in market competition. The most critical point of IDM 2.0 is that Intel needs to change its business strategy from pure IDM to Foundry. Samsung and GlobalFoundries have completed this transformation. GlobalFoundries has become a pure foundry similar to TSMC, while Samsung has split into product and foundry service companies, similar to the model Intel is pursuing.

Intel has previously tried to provide foundry services to external manufacturers, but its actual competitiveness is limited. The problem is not just the price. If you want to use Intel's foundry services, you need to use its proprietary design tools, and Intel is unwilling to modify the manufacturing process for individual products, which basically excludes those cost- and power-sensitive applications. Under the new strategy, Intel began to think and act like foundries like TSMC.

It has to be said that the measures taken by Intel after learning from its mistakes were very effective.

The first shift is that Intel is not only opening up its own fabs, but also Intel's packaging services. Intel has a long history of R&D investments in advanced packaging, was one of the first companies to use multi-chip modules, demonstrated the ability to stack chips through through silicon vias (TSVs), and is leading the use of glass substrates for future high-performance applications. In the past, companies wanted to take advantage of Intel's expertise in packaging, but Intel turned down these businesses unless all chips were manufactured at the same time. Opening up its advanced packaging capabilities is Intel's initial foundry revenue growth point under IDM 2.0, and is accompanied by additional packaging capacity investments in existing facilities in New Mexico and Malaysia, especially its embedded multi-die interconnect (EMIB) and 3D Foveros packaging capabilities, as well as new facilities in Poland.

The second shift is to deliver new process technology and restore Intel to competitiveness and ultimately leadership. To achieve this goal, Intel has committed to delivering five new process nodes in four years. At this year's Intel Direct Connect conference, Intel delivered on this promise and launched the fifth process node 18A. In addition, the company announced the sixth major process node 14A and introduced several specialized sub-nodes, which are common in foundries to meet the various needs of different products and applications.

Intel also further discussed how it compares to other leading foundries in each process node and advanced packaging to show where it currently stands in the competition and when it will surpass its competitors. According to Intel, the 18A process node will put the company back in the lead in high-performance computing (HPC) applications, even surpassing competitors in some cases. Intel believes that the 14A generation will put the company ahead of competitors in mobile applications as well. Intel plans to return to the normal cadence of one process node every two years.

The third shift is the increase in investment in manufacturing capacity and the change in the way investment is managed. As governments look to ensure future supply security and economic growth in the semiconductor manufacturing industry, Intel has invested heavily in existing facilities in Oregon, Ireland, and Israel, and has built six new fabs in Arizona, Ohio, and Germany. Most of the initial investment was made without government subsidy commitments, such as the US Chip Act. However, Intel has now received more than $50 billion in US and European government incentives, customer commitments (starting with the first five 18A process node customers), and financial partners. Intel also received an $11 billion loan from the US government and a 25% investment tax credit.

In addition to its own capacity investments, Intel is also working with Tower and UMC, two long-established and successful foundries. Tower will invest in new equipment installed in Intel's New Mexico facility to produce analog products, while UMC will work with Intel to utilize three older factories and process nodes in Arizona, starting with 12nm, to support applications such as industrial IoT, mobile, communications infrastructure and networking.

The other side of the investment is how current and future capacity is used. As a pure IDM, Intel has historically capitalized its physical facility investments by revamping its fabs every three process node generations on average. While this allows for the reuse of structures and infrastructure, it eliminates support for older process nodes, which is very important to many foundry customers. According to Omdia Research, less than 3% of all semiconductors are produced at the latest process nodes. As a result, Intel is shifting from revamping fabs to support new process nodes to maintaining fabs to support the extended lifecycle of older process nodes, as shown in the figure below. This requires additional capacity for new process nodes.

It is worth noting that one fab can support multiple process nodes. There is a high degree of equipment reuse between process nodes. The difference is the number of steps in one process versus another, such as immersion lithography versus EUV lithography. However, some process node transitions require higher investments in new capacity, such as the transition of the 14A node due to the introduction of High-NA lithography. Intel believes that new capital investments will peak by 2024. The result will be lower investments and higher returns starting in 2025, especially as new customers begin to take advantage of Intel's older and fully depreciated process nodes.

The fourth shift, and the most impressive, is Intel's rapid move to support industry-standard electronic design automation (EDA) tools. As noted at Direct Connect, Intel now supports all industry-standard EDA tools from companies such as Ansys, Cadence, Siemens, and Synopsys. This is critical to simplifying the use of Intel foundry services. It also overcomes one of the biggest barriers for other semiconductor suppliers not to use Intel as a foundry in the past.

The fifth transformation is the completion of the separation of the wafer manufacturing division, which has now become Intel Foundry. Intel announced this week a new reporting structure for Intel Foundry, including financial restatements back to 2021, the development of a unified charging model to serve internal and external customers, and provided future revenue and earnings forecasts for Intel products and Intel Foundry Group. Financial data shows that Intel Foundry will continue to lose money in the short term, but Intel believes that by 2030, Intel products (60% gross profit margin/40% operating profit margin) and Intel Foundry (40% gross profit margin/30% operating profit margin) will achieve higher profitability.

One benefit of using Intel's foundry for external customers is that the process has been fully tested and mass-produced for Intel products. This should significantly reduce the production ramp-up time for external customers. Intel predicts that by 2030, external customers' revenue will reach $15 billion in advanced packaging, advanced EUV process nodes, and older process nodes, and each link will have strong profit margins. As a result, Intel believes that it will return to double-digit ROI by 2030.

The final shift is Intel's understanding of being a foundry. Intel does more than just provide chip manufacturing and assembly services to external customers. Intel sees it as a system foundry that will provide a variety of services, leveraging a wide range of engineering expertise from semiconductor process technology to system development. As Intel CEO Gelsinger said, "racks are becoming systems, and systems are becoming chips." As the performance demands of generative AI workloads continue to increase, the need to put processing, storage, and networking together will increase. Foreign agency Tirias Research believes that by 2030, our concept of chips will change dramatically. At the highest performance, a "chip" may be a single package that requires 2,000 watts or more of power. This will completely change the way we think about system architecture.

Although there is still a long way to go to achieve the goals of Intel's IDM 2.0 strategy proposed in 2021, Intel has already fulfilled some of its promises and is on the road to becoming a world-class leading semiconductor foundry service. At present, Intel, which has both advanced processes and advanced packaging, is likely to become one of TSMC's future rivals.

Nvidia is the biggest winner in the AI ​​wave, and TSMC, which dominates the manufacturing of data center computing engines, has also made a fortune. Today, almost all CPUs, GPUs, DPUs, XPUs and FPGAs are produced by this Taiwanese company.

In the second quarter of 2024, TSMC's revenue increased by 32.8% to US$20.82 billion, net income increased by 29.2% to US$7.66 billion, and 3nm process revenue reached US$3.12 billion, a year-on-year increase of 83.9%.

Specifically in the market segments, HPC business revenue exceeded US$10 billion for the first time, a year-on-year increase of 57% to US$10.83 billion, and a month-on-month increase of 24.7%; smartphone business revenue reached US$6.87 billion, a year-on-year increase of 32.8%, but a month-on-month decrease of 4.2%; 5nm technology (including N5 and N4 processes) revenue was US$7.29 billion, a year-on-year increase of 55% and a month-on-month increase of 4.4%; 7nm revenue fell 1.8% to US$3.54 billion, a month-on-month decrease of 1.3%; other old process chip revenue was US$6.87 billion, accounting for one-third of total revenue.

It can be seen from the financial report that TSMC's market demand is mainly driven by smartphones and high-performance computing (HPC) businesses. Although the smartphone business experienced a downturn in 2023, it rebounded in 2024, which provided financial support for TSMC's future investment. The growth of the HPC business, especially the demand for AI training and inference chips, has driven TSMC's continued investment and technological innovation in this field.

At present, TSMC's investment in AI and HPC is gradually showing results. Although TSMC has not disclosed specific AI-related revenue, it is expected to account for at least 9% of total revenue, about US$1.87 billion, and about 17% of HPC revenue. This includes not only advanced process foundry, but also the popular advanced packaging. TSMC plans to further expand CoWoS (silicon interposer integration) packaging capacity in 2026 to meet market demand. From 2023 to 2024, TSMC's CoWoS packaging capacity has doubled, and it is expected to double again by 2026.

Wei Zhejia also elaborated on the new Foundry 2.0 strategy at the conference. He said: "TSMC's mission is to become a trusted technology and production capacity provider for the global logic IC industry. The continued growth in AI demand supports the strong structural demand for energy-efficient computing. As a key enabler of AI applications, customers rely on TSMC to provide the most advanced process and packaging technologies. We adopt a rigorous framework to respond to long-term market demand, focusing on major industry trends such as AI, HPC and 5G. Our capital investment decisions are based on technological leadership, flexible manufacturing, customer trust and sustainable and healthy returns. To ensure an appropriate return on investment, we make strategic adjustments in pricing and costs. TSMC is investing heavily in leading professional and advanced packaging technologies to support customer growth and ensure our position as a trusted foundry partner."

Why did TSMC, the leading foundry company, propose such a new strategy? Part of the reason may be risk avoidance. After all, TSMC's share in the foundry market has reached a monopoly point. A 61.7% share means that all other manufacturers combined do not make as much as it does. On the other hand, this strategy also expands its growth space. In 2023, the pure foundry market will only be US$115 billion, but the foundry market in a broad sense, including packaging, will be US$247.5 billion. This bigger pie also makes it easier for TSMC to "draw the pie": how to continue to increase sales and maintain or even expand profitability in the next few years.

As Moore's Law slows down, everything in the semiconductor industry is becoming more expensive, and profitability has been a challenge. From 2005 to now, TSMC has been able to bring an average of 35% of revenue into profit, and from the second half of 2021 to the first half of 2023, TSMC has achieved an even better performance, with an average profit of 41.6%.

But since the second half of 2023, TSMC's profitability has been on a slightly downward trend, and it must look for new profit growth points, which is why we have been hearing rumors that TSMC will increase the prices of its manufacturing and packaging services.

For TSMC, it is necessary to ensure the safety of advanced processes and to expand the market in advanced packaging. Foundry 2.0 may seem to be a slogan shouted by TSMC, but in fact it is the foundry's clear understanding of itself - customer-oriented and seizing every possible point in the market. The development of CoWoS packaging from concept to implementation also relies on this understanding.

Interestingly, this is not the first time that TSMC has called out the 2.0 slogan. As early as 2000, TSMC launched TSMC-Online 2.0, the first personalized Internet information service for foundry customers. As a new function for conducting business transactions, TSMC-Online 2.0 has a one-stop tape-out service, enabling customers to shorten actual production time and provide customers with the latest process status control.

We don’t know what TSMC’s next 2.0 will be, but Foundry 2.0 is not good news for its foundry competitors.

Although Samsung did not throw out the concept of "XX 2.0" like Intel and TSMC, Samsung has already shouted out its own slogan for the foundry market.

As early as the SAFE Forum held in San Jose in October 2022, MJ Noh, head of the design services team at Samsung Foundry Headquarters, announced Samsung Foundry's new goals in his speech.

It points out that as technology develops, it becomes increasingly difficult to adopt a "one-size-fits-all" approach. Great ideas should not be limited by the pursuit of a one-size-fits-all solution. However, companies need to be free to pursue their ambitions, so they need a foundry they can rely on that can provide them with the insight and flexibility to meet a variety of needs, even the most unique innovation needs. In a future where cutting-edge technology continues to break boundaries - from cars to mobile devices, from the Internet of Things to high-performance computing and artificial intelligence - is it possible to build a foundry that can unify everything in one place?

Among them, MJ's speech covered how Samsung's advanced design platform uses technologies such as 2.5D and 3D solutions to provide customers with a one-stop service that can adapt to the scale and specific requirements of future creativity.

At the previous forum, Samsung focused on the strong and extensive capabilities of its design platform in multiple fields such as automobiles, mobile devices, IoT and artificial intelligence, including AEC-Q100 certification and ASIL standard preparation in the automotive field. At the same time, the growth rate of high-performance computing applications is particularly fast, and the foundry industry is looking for dynamic modularization of core grain architecture to find answers. In all these areas, Samsung always focuses on customer priorities when seeking cooperative platforms: accelerating time to market through optimized production cycles and competitive power, performance and area (PPA) capabilities such as design technology co-optimization (DTCO) and system technology co-optimization (STCO). Ultimately, foundries need to have the ability to provide one-stop cutting-edge design capabilities without third-party specialization. Of course, providing all this is not easy.

“Traditional chip design approaches face limitations due to high cost and integration factors,” said MJ. “Even with silicon scaling, transistor counts are still increasing, pushing the limits of the maximum available mask size, while the demand for chips that integrate multiple functions continues to rise, which creates serious cost issues in design and manufacturing.”

He explained that shrinking transistor size will never keep up with the growing complexity of applications, which is why Samsung is leading the way with its ever-advancing 2.5D and 3D chiplet solutions.

More than two years after the one-stop service was proposed, this solution began to shine because of AI.

According to recent reports from Korean media, Samsung has begun to attract domestic fabless (companies focusing on semiconductor design) customers based on its "one-stop" artificial intelligence solution strategy. Samsung uses its advantages in memory, foundry (semiconductor foundry production), packaging, etc. to provide customized AI one-stop solutions. In particular, it strives to attract potential customers by strengthening cooperation with design solution partners (DSPs).

On July 9, Samsung Electronics unveiled its achievements and future support plans for strengthening the domestic system semiconductor ecosystem at the "Samsung Foundry Forum (SFF) 2024 and SAFE (Samsung Advanced Foundry Ecosystem) Forum 2024" held at Coex in Seoul.

Choi Si-young, head of Samsung Electronics’ foundry business, said: “As the impact of AI on products increases, the number of featured customers is also increasing. These customers want to realize various ideas through semiconductors.” He explained: “These customers not only need individual solutions such as design, design assets (IP), process, and packaging, but also services that integrate the entire system-level verification.”

Therefore, Samsung Electronics plans to leverage the strengths of an integrated semiconductor company (IDM) to provide a one-stop service for integrated AI solutions that meet customer needs. By strengthening cooperation between the three major business areas of memory, foundry, and packaging, the "Lock-In effect" can be maximized to prevent customers from losing during the product production process. Fabless customers can reduce semiconductor development and production time by 20% by using Samsung's integrated AI solutions.

In particular, the company will strengthen its advanced process services below 3 nanometers (nm, one billionth of a meter) based on the competitiveness of the gate all around (GAA) process and 2.5D packaging technology. GAA is a new generation technology that increases the contact surface of the transistor gate (the gate for current in and out) and channel (the path for current flow) in semiconductors to four, which allows faster data processing and higher power efficiency than FinFET technology. Samsung Electronics successfully mass-produced the 3nm process using GAA for the first time in June 2022, and is currently smoothly advancing the second-generation 3nm process.

In addition, Samsung Electronics will actively support Korea's excellent fabless companies to rapidly expand their influence in the fields of high-performance computing (HPC) and AI. DSP provides foundry manufacturing design services for semiconductors designed by fabless companies. That is, by strengthening the cooperation between "Samsung Foundry-DSP-fabless", potential customers can be attracted.

Cooperating with DSP company Gaon Chips, Samsung Electronics successfully obtained the order for 2nm (SF2)-based AI accelerator from Japan's Preferred Networks (PFN), which is a representative achievement of Samsung Electronics' cooperation with domestic DSPs. Samsung plans to mass-produce Japan's Preferred Networks' AI accelerator semiconductors based on 2nm process and 2.5D advanced packaging (I-Cube S).

In addition, Samsung Electronics announced that it will expand its multi-project wafer (MPW) service to support domestic fabless companies. MPW is a product development method that places multiple project chip designs on a single wafer, mainly for prototyping or research purposes. Fabless companies do not have their own production lines, so they must use foundries for prototyping. Through MPW support, Samsung Electronics hopes to attract potential fabless customers in advance.

This year, Samsung Electronics' MPW service number has increased by about 10% from last year, from 4nm process to BCD 130nm process for producing high-performance power semiconductors, to 32 times. It is planned to expand to 35 times by 2025. The 4nm process, which has high demand, will be increased once more this year.

During the event, Telechips President Lee Chang-gyu, Above Semiconductor Vice President Park Ho-jin, Rebellions Chief Technology Officer (CTO) Wu Zhenxu and others served as speakers and shared the successful cooperation results, vision and fabless industry trends with Samsung Foundry.

Choi Si-young emphasized: "Samsung Electronics can integrate memory, foundry and packaging manufacturing capabilities into one organization. Based on this advantage, we will provide customers with the most efficient and optimized solutions."

Compared with Intel and TSMC, Samsung's foundry performance has not been impressive enough in the past two years due to repeated obstacles in advanced processes. It is somewhat overshadowed by the two giants that have launched the 2.0 slogan.

But Samsung also has its own advantages. After Intel abandoned Optane memory, it is the only foundry that can provide memory, manufacturing and packaging. For small and medium-sized enterprises that are growing rapidly due to AI, it can provide advantages that other companies do not have.

However, the only drawback is that Samsung's current HBM business is not satisfactory. It seems to have become a mediocre player. Although it is not outstanding in all aspects, it still has good technical strength. How to make itself outstanding in the fields it is good at and not good at may be a problem that this Korean company needs to think about.

Whether it is TSMC, Intel, or Samsung, they are all betting heavily on foundry. Intel plans to increase capital expenditure by 2% to US$26.2 billion in 2024; TSMC's capital expenditure this year is expected to be between US$28 billion and US$32 billion. Samsung's capital expenditure on semiconductors in 2023 reached US$37.268 billion.

There are also reports that TSMC's capital expenditure this year will reach the upper limit of the estimated range, and the upper limit is expected to increase by another US$5 billion next year to US$37 billion, which is expected to set the second highest level in history. The huge expenditure makes it difficult for other companies to match.

With the slowdown of Moore's Law, the war among foundry giants seems to have reached a white-hot stage. The endless new strategies and continuous capital outflow are constantly increasing the intensity of this war. The final criterion for testing the winners and losers is also very simple. Whoever can continue to expand their market share in the next few years will represent the future and the real foundry 2.0.

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