Interpretation of Intel's PowerVia technology

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A major challenge in semiconductor design is powering transistors. A chip can have up to 18 layers of metal, powering the device and receiving signal input and output. Tall metal stacks extend power lines, increasing voltage drop and parasitic capacitance. This will either slow down the chip or require more power to maintain the frequency.

To reduce stack height, semiconductor manufacturers are moving power delivery to the backside of the chip. Lower signal stack height reduces resistance and capacitance, while shorter power lines have lower resistance.

Two years ago, Intel revealed its approach - power via PowerVia (see MPR August 2021, "Intel expands process roadmap to 20A"). Intel plans to introduce PowerVia into its 20A process and plans to put it into production at the end of 2024. At the 2023 IEEE VLSI Technology and Circuits Symposium held in June, Intel published three papers disclosing more details: one about the process itself [1], and the other results from a test micro processor[2], the third result looks at the possible evolution of PowerVia[3].

Intel reports that PowerVia reduces IR-Drop by approximately 30%, increases frequency by 5%, and increases cell density to 90% due to the elimination of power rail space.

Intel differentiates its PowerVia backside power delivery (BPD) from the buried power rail (BPR) architecture discussed by Imec and others over the past few years. In the BPR configuration, power comes from the front metal, but it reduces unit height by burying the power rails parallel to the fins (instead of using M1).

While this helps deliver power to the unit and helps with scaling, it still faces large IR drops and routing challenges from front-end cabling. The evolution of BPR includes BPD. BPR alleviates IR-Drop of the front-end power stack and improves routing in standard cells. However, there is still some routing congestion as connections to lower metal layers still need to be made.

In contrast, Intel's PowerVia uses Deep Via Passthrough (DVP: Deep Via Passthrough) to provide a direct power connection to the transistor. This eliminates all power transfer to the lower front metal layer in a standard cell, maximizing the gain of the BPD, as shown in Figure 1.

Figure 1 Rear power supply method

(BM = Backside Metal. On the left, Buried Power Rail (BPR) architecture still uses power delivery on the front. In the middle, BPR with Backside Power Delivery (BS-PDN) requires partial front metal ization. On the right, the PowerVia's deep via directly connects to the transistor contacts (Image credit: Intel; additional note: TechInsights))

To decouple potential issues not related to 20A integration, Intel developed PowerVia using its Intel 4 process, creating an intermediate process that combines Intel 4's FinFETs with DVP and BPD processes from its 20A generation RibbonFET gate-all-around (GAA) technology. modules (see MPR, May 2023, “Gate-All-Around increases logic speed”). The company created a library of intermediate cells containing DVP to implement contacting of a pair of contact strips in one cell.

Compared with native Intel 4, the PowerVia enhanced version supports relaxing the M0 pitch from 30nm to 36nm and removing the front-side metal layer (as shown in Table 1), thus simplifying lithography and reducing front-side costs. The BPD has five wide metal layers that provide power to the DVP. These add cost but do not require complex photolithography.

Table 1 Comparison of PowerVia between Intel 4 and Intel 4+

(Using PowerVia can relax the M0 spacing, reduce the signal metal layer, and reduce the unit height. (Data source: Intel))

As shown in Figure 2, by removing two fins and adding DVP, the high-performance (HP: High Performance) standard cell height shrinks from 240nm to 210nm, and the logic density increases proportionally.

Figure 2 Modified cell library for Intel 4 process using PowerVia

(In a modified standard cell, the DVP trench connects to a pair of contact trenches. (Image: Intel; Additional note: TechInsights))

Figure 3 shows a full stack cross-section of the test chip. The thick, low-resistance metal on the lower (back) side should have reduced IR drop compared to the front-end power routing, which has to go down a stack of tapering wires as it gets closer to the transistor.

The high-magnification image on the right shows the transistor and the DVP between the two metal stacks; the DVP is the trench metallization running lengthwise into the image. In this diagram, DVP is not connected to the transistor contacts.

Figure 3. TEM cross-section of PowerVia metallization

(On the left is an image of the front and back metal stacks. The image on the right is at higher magnification and shows the DVP in more detail. They do not coincide with the spacing of any of the front metal layers. (Image: Intel, Comment: TechInsights))

Creating PowerVia devices requires two different process sequences using two wafers, as shown in Figure 4. Initially, Intel 4 transistor manufacturing used normal processes until contacts were formed. After etching, metal fill and planarization steps, the vias are coplanar with the contacts; a standard metallization sequence then creates the signal stack. There is a sealing layer on the wafer.

DVP exposure begins by bonding the carrier wafer to the seal on the original wafer, flipping the combination, and then polishing the backside of the original wafer to expose the via metal and the bottom of the transistor fins. Next, oxide deposition is performed and the PowerVia backside metal stack is created. The carrier wafer still provides strength to the final chip.

Figure 4 PowerVia process sequence

(a) After standard transistor formation, the DVP is coplanar with the contact metallization layer. b) The signal metal stack is on top of the transistor/DVP layer and sealed. c) After flipping, the front side stack is on top of the carrier wafer and the original substrate is polished to expose the DVP and fin bottom. d) The back side metal establishes a connection with DVP. (Image: Intel, additional notes: TechInsights))

Intel's paper does not discuss contact metallization. If the contacts are made of the same metal as the DVP, the company may cut the source/drain contact trenches first and then the DVP trenches. Next, it applies a common metal fill (looks like tungsten in the Figure 3 image) and then polishes the two trench fills back to coplanarity.

It is worth noting that Intel created silicon-on-insulator (SoI) FinFET, a technology used only by IBM so far; in pursuit of lower IR-Drop, Intel created a radiation-hardened process.

Transistor performance shows no difference between PowerVia and the reference Intel 4 process. Id-Vg and Id-Vd characteristics match on NMOS and PMOS devices. The same applies to reliability: time-dependent dielectric breakdown, bias temperature instability (BTI) and hot carrier injection measurements are all similar, and electromigration testing of DVP shows strong performance.

Since there is no substrate silicon to dissipate heat, the backside metal may present thermo-mechanical reliability issues, but PowerVia meets all standard JEDEC stress requirements.

Intel用于PowerVia评估的测试器件名为Blue Sky Creek，基于即将推出的Meteor Lake处理器中使用的Crestmont CPU。Blue Sky Creek在33.2mm ² 芯片中包含四个核心以及其他实验测试电路，例如热测试结构；该测试封装包含两个管芯Die构成了66.4mm ² 的测试芯片，如图5所示。核心目标最大频率(Fmax)为1.1V下3GHz。

图5 Blue Sky Creek测试芯片和封装

（用于PowerVia评估的测试芯片位于左侧，测试封装位于右侧。（图片：Intel））

与采用标准Intel 4工艺的Crestmont CPU相比，从前端移除电源线，信号线长度减少了20%，信号过孔数量减少了约5%，从而提高了布线质量。它还导致EDA工具插入更少的反相器和缓冲器，从而实现更高的频率、更低的动态功耗和更低的漏流。

更简单的正面金属（减少）的另一个结果是消除了由（以前的）电源金属堆叠引起的可靠性问题，这使得可靠性收敛得更快。设计规则检查更加简单，即使单元密度更高并因此导致额外的布线拥塞。改进的布线质量允许有更多的时间进行优化，从而使核心大面积的逻辑单元密度超过90%，同时最大限度地减少未使用的芯片面积。Intel表示，修改2200万门CPU的物理设计花了三个月的时间。

仿真显示，从晶圆凸块到晶体管，背面电源金属的IR压降下降了5倍。在测试芯片中，与Intel 4参考器件相比，片上监视器展示从封装到晶体管的IR-Drop降低了30%以上。因此，修改后的核心实现了6%的频率提升，并且电源传输频率压力测试证明速度提高了6.7%。

由于担心新技术的热效应，该设计将30%的核心区域用于监控温度的结构，因为标准Intel 4和 PowerVia部件的功耗都会增加。热响应与工艺缩放预期的功率密度增加一致。

PowerVia评估使用FinFET来证明该技术，但两年前 Intel Accelerated上最初发布的图像显示PowerVia应用于GAA测试器件（大概是Intel 20A工艺下的RibbonFET晶体管），如图6所示。

图6 采用PowerVia的Intel 20A

（左侧是一些正面和背面金属堆叠的图像。右图放大倍数更高，更详细地显示了结构。DVP与最低正面金属层的间距一致，每个晶体管中有四个纳米带nanoribbons。（图片：Intel，注释：TechInsights））

TechInsights最近分析了三星的3nm GAA技术，发现晶体管中有三个纳米片（纳米带），台积电也展示了三纳米片堆叠。Intel可能打算使用四层纳米片来提高驱动电流。

Intel正在探索PowerVia的开发，直接接触源极/漏极外延，而不是沿着晶体管触点。在概念验证研究中，Intel开发了一种背面接触工艺 (BSCON: Backside Contact Process)，如图7所示。BSCON可实现更紧凑的单元和更低的寄生电容，从而在与非BSCON控制器件相同的功率和面积下提高工作频率。

图7 背面晶体管接触

（TCN=顶部触点Top Contact。b）和c）中带有BSCON的第二代PowerVia直接接触源极/漏极外延。（图片：Intel，经过TechInsights的修改以显示PowerVia连接到TCN。））

Intel在FinFET和RibbonFET上测试了BSCON概念，将正面接触的器件的晶体管与使用 BSCON从背面供电的器件的晶体管进行了比较。Ion-Ioff曲线、阈值电压、亚阈值斜率和DIBL均匹配。同样，PMOS栅极氧化物击穿和负BTI的可靠性研究是等效的，并且电迁移测试未显示任何故障。

展望具有堆叠式PMOS和NMOS晶体管的CMOS，PowerVia加上BSCON为更紧凑的单元提供了潜力，如图8所示。

图8 堆叠的晶体管

（TCN=顶部触点。a）PowerVia与传统并排晶体管；b）BSCON接触一个晶体管的基极，并且（假定）顶部接触另一个晶体管；c）扩展的PowerVia可用于接触堆叠晶体管对的顶部晶体管。（图片：Intel，经过TechInsights的修改以显示PowerVia连接到TCN。））

通过分离信号线和电源线，芯片变得更加节能并获得性能。将电源传输转移到背面可以增加单元密度，加宽下部金属间距，并减少信号金属层的数量。PowerVia堆栈不需要任何EUV光刻，因为其金属间距足够粗，可以使用浸没式光刻进行单次图案化。加上改进的布线质量和不太复杂的设计规则检查所节省的成本，更便宜的UV光刻抵消了实施PowerVia所需的额外处理的成本。Intel预计PowerVia的成本是中性的。

对于Intel 20A生产工艺，Intel计划同时采用背面电源和GAA晶体管。尽管Intel在同时推出应变晶体管和低k电介质时做了类似的事情，但同时引入两个重大变化既困难又危险。为了降低研发阶段的风险，Intel使用其Intel 4工艺开发了PowerVia。同时，它还单独开发了2nm GAA（RibbonFET）晶体管。如果将PowerVia的Intel 4开发工具中看到的优势转移到RibbonFET设计中，那么20A节点应该能够满足其性能目标。

Intel表示，其5N4Y（四年内五个节点）计划已步入正轨，到2025年将重新获得晶体管功率和性能领先地位，并报告其Arrow Lake 20A处理器的第一步已在晶圆厂进行。如果该公司在2024年成功推出Arrow Lake，它将成为业内第一个推出采用背面供电的产品，从而领先竞争对手两年。台积电和三星预计在2026年之前不会推出BPD。如果2024年能够成功将20A投入量产，这对于18A工艺来说将是一个好兆头，而18A工艺技术对于Intel作为代工厂的成功至关重要。

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