TSMC, 1nm

Latest update time：2024-01-22

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TSMC’s one-nanometer factory plan, with an investment of more than one trillion yuan, plans to set up a factory in the Science Park in Taibao City, Chiayi County. This is the third 2-nanometer wafer fab that TSMC announced at the Kaohsiung plant.

According to sources, TSMC has proposed a land requirement of 100 hectares to the Nanke Administration Bureau in charge of the Chiayi Science Park, of which 40 hectares will be used to build an advanced packaging plant, and the subsequent 60 hectares will be used as land for the construction of a one-nanometer factory. Since TSMC's land demand exceeds the 88 hectares planned for the first phase of Chiayi Science Park, it is expected to accelerate the second phase of expansion to facilitate TSMC's entry.

TSMC stated that there are many considerations in selecting a factory location. TSMC uses Taiwan as its main base and does not rule out any possibility. It also continues to cooperate with the Administration to evaluate suitable sites for semiconductor factory construction. TSMC pointed out that for all information, please refer to the company’s external announcements.

Chiayi County Mayor Weng Zhangliang pointed out that he respects TSMC’s decision on where to set up the factory and believes that there will be the best evaluation. He sincerely welcomes TSMC to invest in Chiayi and welcomes outstanding talents to come to Chiayi. He believes that Chiayi County will become the most competitive and developed in the Western Corridor in the next few years. potential city. He also said that Chiayi Science Park currently has sufficient green power and plans to build a desalination plant to create a good base for the development of the industry. The favorable conditions are definitely the first choice.

It is understood that the TSMC factory construction team sent people to conduct factory inspections before the Chiayi Science Park was designated as a science park under the jurisdiction of the Southern Science and Technology Administration in August last year. This was also the case when the third phase expansion of the Longtan Science Park in Taoyuan encountered fierce resistance. Later, the TSMC factory construction team started the registration plan, and finally decided to abandon the factory plan in the Longke Phase III expansion project.

After TSMC gave up the construction of Longtan factory, it immediately attracted the heads of counties and cities including Kaohsiung, Taichung, Changhua, Chiayi, Yunlin, Tainan and Pingtung to woo them to invest. Local governments also stated that they would invest in land, water supply and power supply. Full assistance. Weng Zhangliang stated at that time that if TSMC wanted to go to Chiayi for assessment, he would serve as the convener and form a professional team to fully assist. He also emphasized that there is a lot of Taiwanese sugar land in the county and there will not be any big problems in expropriating it in the future.

However, TSMC has long-term leased land from the Administration Bureau under the jurisdiction of the National Science Council, and both parties established a single window. Finally, they settled on the Chiayi Science Park, mainly because of its favorable geographical location, complete land area, and scalability. This is consistent with Weng Zhangliang’s statement.

The one-nanometer manufacturing process settled in Jiake can diversify regional risks and is also conducive to the urban development of Chiayi County and narrowing the gap between urban and rural areas. Furthermore, the Chiayi Science Park is only seven minutes away from the Chiayi High-Speed Rail Station. It connects TSMC's Zhongke and Zhuke factories to the north, and connects Nanke and Kaohsiung factories to the south. This is in line with what TSMC founder Zhang Zhongmou previously mentioned. Thousands of engineers will be mobilized within a day to support the operations of various factories, making the western Taiwan technology corridor more complete.

According to industry insiders, TSMC announced the expansion of its third 2nm factory in Kaohsiung, the brakes on its second U.S. factory, and the 1nm plant in Chiayi, declaring TSMC’s determination to keep its advanced manufacturing processes in Taiwan.

This move not only expresses to global chip manufacturers that "if you want the most cost-effective and advanced chip foundry, you must come to Taiwan for production." It also shows Samsung and Intel that TSMC has the most complete wafer foundry ecosystem in the world. Strong policy support is needed to shake TSMC’s position as the world’s leading wafer foundry manufacturer. To paraphrase TSMC President Wei Zhejia’s words, “There is no way out!”

TSMC has also planned two 2nm factories

When Taiwan Semiconductor Manufacturing Co. (TSMC) prepares to launch a new process technology, it typically builds a new fab to meet the needs of its alpha customers and then adds capacity by upgrading the existing fab or building another fab. For N2 (2nm), the company appears to be taking a slightly different approach, as it has already built two N2-capable fabs and is awaiting government approval for a third.

We are also preparing to start mass production of N2 from 2025," TSMC's outgoing chairman Mark Liu said during the company's earnings call with financial analysts and investors. "We plan to build multiple wafer fabs in Hsinchu and Kaohsiung Factory or multi-phase 2nm technology science park to support customers' strong structural needs. […] “At the Taichung Science Park, the government approval process is underway and on track.”

TSMC is preparing to build two manufacturing plants in Taiwan capable of producing N2 chips. The first wafer fab is planned to be located near Baoshan, Hsinchu County, adjacent to the R1 R&D center, which is specially built for the development of N2 technology and its follow-up technologies. The factory is expected to begin high-volume manufacturing (HVM) 2-nanometer chips in the second half of 2025. The second manufacturing facility with N2 capabilities will be located in the Kaohsiung Science Park, part of the Southern Taiwan Science Park near Kaohsiung. Start-up of the plant's HVM is expected to be somewhat later, probably around 2026.

Additionally, the foundry is working to obtain government approval to build another N2-capable fab in the Taichung Science Park. If the company starts construction of the plant in 2025, the plant could be operational as soon as 2027.

TSMC has three fabs capable of manufacturing chips using its 2nm process technology and is preparing to deliver huge 2nm production capacity in the coming years.

TSMC expects to launch HVM around the second half of 2025 using its N2 process technology, which uses gate-all-around (GAA) nanosheet transistors. TSMC's second-generation 2nm-scale process technology - N2P - will increase backside power transfer. The technology will reach mass production in 2026.

What will chips after 1nm rely on?

There is no doubt that the next generation of CMOS logic will enter the 1nm era at the upcoming IEDM. There are many famous lectures on "next generation CMOS". Therefore, we divide them into the "Complementary FETs", "2D Materials" and "Multilayer Wiring" subcategories.

In this article, they are introduced in order.

Stack the two FETs that make up CMOS to reduce the silicon area in half

The first is "Complementary FETs (CFETs)" in the field of "next generation CMOS logic". CMOS logic (logic circuit) consists of at least two transistors: an n-channel MOS FET and a p-channel MOS FET. The logic circuit with the smallest number of transistors is the inverter (logic inverting circuit), which consists of 1 n-channel MOS and 1 p-channel MOS. In other words, it requires the silicon area equivalent to two transistors.

CFET is a three-dimensional stack of these two types of MOSFETs. In theory, CMOS logic could be created using the silicon area occupied by one FET. Compared with traditional CMOS, the silicon area is halved. However, the manufacturing process is quite complex, with many challenges, making it difficult to build.

At IEDM 2023, CFET research and development made significant progress. Both TSMC and Intel have introduced CMOS circuits with monolithically stacked lower-layer FETs and upper-layer FETs. TSMC demonstrated a CFET prototype that monolithically stacked n-channel FETs on top of p-channel FETs. All FETs have a nanosheet structure. The gate pitch is 48nm. The manufacturing yield is over 90%. The current on/off ratio exceeds 6 digits.

Intel designed a CFET prototype that monolithically stacked three n-channel FETs on top of three p-channel FETs (29-2). All FETs have a nanoribbon structure (basically the same structure as a nanosheet structure). We prototyped a CMOS inverter with a gate pitch of 60nm and confirmed its operation.

Using two-dimensional materials to make GAA-structured nanosheet channels

下一代 CMOS 逻辑晶体管的另一个有希望的候选者是通道是过渡金属二硫属化物 (TMD) 化合物的二维材料（单层和极薄材料）的晶体管。当 MOSFET 的沟道尺寸缩短时，“短沟道效应”成为一个主要问题，其中阈值电压降低且变化增加。减轻短沟道效应的一种方法是使沟道变薄。TMD很容易形成单分子层，原则上可以创建最薄的通道。

TMD 沟道最初被认为是一种用于小型化传统平面 MOSFET 的技术（消除了对鳍结构的需要）。最近，选择TMD作为环栅（GAA）结构的沟道材料的研究变得活跃。候选通道材料包括二硫化钼（MoS 2 ）、二硫化钨（WS 2 ）和二硒化钨（WSe 2 ）。

包括台积电等在内的联合研究小组开发了一种具有纳米片结构的n沟道FET，其中沟道材料被单层MoS2取代。栅极长度为40nm。阈值电压高，约为1V（常关操作），导通电流约为370μA/μm（Vds约为1.0V），电流开关比为10的8次方。

imec 和 Intel 的联合研究团队使用二维沟道候选材料在 300mm 晶圆上制造了原型 n 沟道 MOS 和 p 沟道 MOS，并评估了它们的特性。候选材料有 MoS 2 、WS 2 和 WSe 2 。MoS 2 单层膜适用于n沟道FET，WSe多层膜适用于p沟道FET。

包括台积电等在内的联合研究小组开发出一种二维材料晶体管，其电流-电压特性与n沟道FET和p沟道FET相同。MoS 2 （一种 n 沟道材料）和 WSe 2 （一种 p 沟道材料）在蓝宝石晶圆上生长，并逐个芯片转移到硅晶圆上。此外，英特尔还原型制作了具有GAA结构的二维材料沟道FET，并在n沟道和p沟道上实现了相对较高的迁移率。

石墨烯、钌和钨将取代铜 (Cu) 互连

多层布线是支持CMOS逻辑扩展的重要基础技术。人们担心，当前流行的铜（Cu）多层互连的电阻率将由于小型化而迅速增加。因此，寻找金属来替代 Cu 的研究非常活跃。候选材料包括石墨烯、钌 (Ru) 和钨 (W)。

台积电将宣布尝试使用石墨烯（一种片状碳同素异形体）进行多层布线。当我们制作不同宽度的互连原型并将其电阻与铜互连进行比较时，我们发现宽度为15 nm或更小的石墨烯互连的电阻率低于铜互连的电阻率。石墨烯的接触电阻率也比铜低四个数量级。将金属离子嵌入石墨烯中可以改善互连的电性能，使其成为下一代互连的有前途的材料。

imec 制作了高深宽比 (AR) 为 6 至 8、节距为 18 nm 至 26 nm 的 Ru 两层精细互连原型，并评估了其特性。制造工艺为半镶嵌和全自对准过孔。在AR6中原型制作宽度为10 nm（对应间距18 nm至20 nm）的Ru线测得的电阻值低于AR2中模拟的Cu线的电阻值。

应用材料公司开发了一种充分利用 W的低电阻互连架构。适用于2nm以上的技术节点。我们充分利用 W 衬垫、W 间隙填充和 W CMP（化学机械抛光）等基本技术。

将存储器等元件纳入多层布线过程

一种有些不寻常的方法是研究多层互连过程（BEOL）中的存储器等构建元件。多层布线下面通常是 CMOS 逻辑电路。因此，理论上，BEOL 中内置的元件不会增加硅面积。它是提高存储密度和元件密度的一种手段。

斯坦福大学和其他大学的联合研究小组将提出在多层逻辑布线工艺中嵌入氧化物半导体 (OS) 增益单元晶体管型存储元件的设计指南。操作系统选择了氧化铟锡 (ITO) FET。我们比较了 OS/Si 混合单元和 OS/OS 增益单元。

imec 开发了 MRAM 技术，可将自旋轨道扭矩 (SOT) 层和磁隧道结 (MTJ) 柱减小到大致相同的尺寸。它声称可以将功耗降低到传统技术的三分之一，将重写周期寿命延长10的15次方，并减少存储单元面积。

加州大学洛杉矶分校率先集成了压控 MRAM 和 CMOS 外围电路。MRAM的切换时间极短，为0.7ns（电压1.8V）。原型芯片的读取访问时间为 8.5ns，写入周期寿命为 10 的 11 次方。

将计算功能纳入传感器中

我还想关注“传感器内计算技术”，它将某种计算功能集成到传感器中。包括旺宏国际在内的联合研究小组将展示基于 3D 单片集成技术的智能图像传感器。使用 20nm 节点 FinFET 技术，将类似于 IGZO DRAM 的存储层单片层压在 CMOS 电路层的顶部，并在其顶部层压由二维材料 MoS 2 制成的光电晶体管阵列层。光电晶体管阵列的布局为 5 x 5。

西安电子科技大学和西湖大学的联合研究小组设计了一种光电神经元，由一个光电晶体管和一个阈值开关组成，用于尖峰神经网络。对连续时间内的传感信号（光电转换信号）进行压缩编码。

在硅晶圆上集成 GaN 功率晶体管和 CMOS 驱动器

对于能带隙比 Si 更宽的化合物半导体器件（宽禁带器件），在 Si 晶圆上制造氮化镓 (GaN) 基 HEMT 的运动十分活跃。英特尔在 300mm 硅晶圆上集成了 GaN 功率晶体管和 CMOS 驱动器。CMOS驱动器是GaN增强型n沟道MOS HEMT和Si p沟道MOS FET的组合。用于GaN层的Si晶片使用面。对于 Si MOS FET，将另一个面的硅晶片粘合在一起，只留下薄层，用作沟道。

CEA Leti developed AlN/GaN/Si MIS-HEMT for Ka-band power amplifiers (38-3). Compatible with 200mm wafer Si CMOS process. The HTMT prototyped by optimizing the SiN gate insulating film has an ft of 81GHz and an fmax of 173GHz. The PAE (power load efficiency) at 28GHz is extremely high, reaching 41% (voltage 20V). Assume we have achieved performance comparable to GaN/SiC devices.

A small CMOS image sensor with 64 million pixels and a pixel size of 0.5μm square.

In image sensors, notable results include increases in pixel count, reductions in pixel size, noise reduction, and advances in autofocus functionality. Samsung Electronics has trial-produced a high-resolution CMOS image sensor with 64 million pixels and a small pixel size of 0.5 μm square.

Three silicon wafers are stacked using hybrid bonding with copper electrodes and connected to a photodiode and subsequent circuitry for each pixel. Compared with conventional models, RTS (Random Telegraph Signal) noise is reduced by 85% and FD (Floating Diffusion) conversion gain is increased by 67%.

OmniVision Technologies has developed an HDR global shutter CMOS image sensor with a pixel pitch of 2.2μm. It is made by gluing two pieces of silicon together. FPN (fixed pattern noise) is 1.2e-(rms value) and temporal noise is 3.8e-(rms value).

Canon has unveiled a prototype of a dual-pixel crossed CMOS image sensor in which a pair of photodiodes are arranged with a 90-degree twist. Performs autofocus (AF) with omnidirectional phase difference detection. AF's minimum illumination is as low as 0.007 lux.

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