[Shishuo Design] Introducing the next generation of software defined radio (SDR) transceiver with significant frequency hopping (FH) advantages~

Table 1. ADRV9002 Frequency Hopping Modes Based on PLL Usage

As shown in Table 1, the selection of one of the two modes is determined by the user-defined transition time.

Figure 4 further explains the PLL multiplexing mode concept. As mentioned earlier, each time slot represents a skip frame, which consists of a switching period and a dwell period. When one PLL is used during the dwell time, the other PLL starts tuning from the beginning of the switching time of the same skip frame. It can keep tuning until the end of the switching period of the next skip frame. Therefore, as long as the required PLL tuning time is shorter than the sum of one dwell time and two switching times, the PLL multiplexing mode is successful.

Figure 4. PLL multiplexing mode for fast frequency hopping.

Frequency hopping in PLL multiplexing mode is critical for military applications such as Link 16. Link 16 is considered one of the most important tactical data link standards used by the North Atlantic Treaty Organization (NATO) and uses an interference-resistant, high-speed digital data link in the 960 MHz to 1.215 GHz RF band. ³ The ADRV9002 uses a fast PLL re-tuning mode to meet stringent timing requirements by accurately calibrating the entire frequency hopping range at initialization. The PLL re-tuning time depends on the ADRV9002 PLL reference clock rate. Table 2 shows the fast PLL re-tuning time required at different PLL reference clock rates. The fast PLL re-tuning time is approximately 15 μs for a PLL reference clock rate of 300 MHz. With a Link 16 frame hopping length of 13 μs, if the transition time is greater than 2 μs, a PLL re-tuning time of 15 μs can meet the timing requirements when using PLL multiplexing mode, as shown in Table 1.

Table 2. When using fast PLL retuning mode

PLL re-tuning time

As described in the paper "Performance Analysis of JTIDS/Link 16-Type Waveforms Transmitted over Slow, Flat Nakagami Fading Channels in the Presence of Narrowband Interference," Link 16 message data can be sent as a single pulse or a dual pulse, depending on the packetization structure. The single pulse structure consists of a 6.4 μs on time and a 6.6 μs off time, for a total duration of 13 μs. The dual pulse structure consists of two single pulses that transmit the same data but use different carrier frequencies, as shown in Figure 5. Therefore, the transition time is approximately 6.6 μs (>2 μs), making it entirely feasible to implement Link 16 frequency hopping using the ADRV9002.

Figure 5. Standard Link 16 dual-pulse structure.

Figure 6 shows the ADRV9002 transmit output (power vs. time and frequency vs. time) with Link 16 type frame hopping (for simplicity, only transmit frequency hopping is used). Note that in order to show the minimum transition time achievable with the ADRV9002, the experiment did not use the standard Link 16 pulse structure shown in Figure 5, but instead the on time was increased from 6.4 μs to 11 μs and the off time was decreased from 6.6 μs to 2 μs. A Tektronix RSA306B spectrum analyzer was connected to the transmit output port of the ADRV9002 evaluation board for observation. The upper plot shows power vs. time. It can be seen that the transmit frequency hopping occurs every 13 μs, with a transition time of approximately 3 μs between consecutive transmit frame hopping. The lower plot shows frequency vs. time. In this experiment, the transmit carrier frequency cycles between four different frequencies in 1 MHz steps. As expected, the lower plot confirms that the transmit output also cycles between four different frequencies in 1 MHz steps with excellent frequency accuracy throughout the dwell period.

Figure 6. Link 16 Tx frequency hopping transmit output.

The frequency accuracy of Link 16 frequency hopping can be further measured by using more advanced test equipment such as Keysight E5052B and R&S FSWP. In the measurement example shown in Table 3, the transmit carrier frequency hops at 400 MHz, 400.1 MHz, 400.2 MHz, and 400.3 MHz. The transmit input signal also changes frequency synchronously to generate a frequency output of 400 MHz for all hopping frames. The measurement duration is set to 100 μs, which includes 7 complete hopping frames. The frequency is measured every 128 ns. It can be seen that the PLL is completely locked at the beginning of the dwell time. The frequency error during the dwell time depends on the phase noise performance. Table 3 shows the average, maximum, and minimum frequency offset (absolute difference between the output frequency and 400 MHz) performance of these 7 consecutive hopping frames. In most frames, the average frequency error is less than 1 ppm. Dozens of experiments show the same results. Note that the measured values ​​may vary depending on the equipment and test configuration.

Table 3. Frequency accuracy performance of Link 16 frequency hopping

The ADRV9002 also provides the user with the ability to fine-tune the PLL loop filter bandwidth. When the PLL loop filter bandwidth is configured to 1200 kHz, the performance shown in Table 3 can be achieved. A larger PLL filter bandwidth can reduce the PLL re-tuning time and ensure that the PLL is fully locked before the dwell time begins. It is recommended that users further evaluate the required phase noise performance in their application to select the most appropriate loop filter bandwidth.

The ADRV9002 uses a frequency hopping table concept for all frequency hopping modes. Each entry in the frequency hopping table contains the frequency and other operating parameters for the hopping frame. The frequency hopping table can be loaded statically, which means it is loaded during initialization and does not allow for on-the-fly changes thereafter. It can also be loaded dynamically, which is loaded during the execution of frequency hopping; in this case, the user can change the contents of the table on the fly. In addition, a ping-pong-like concept is used so that the user can selectively load two different tables, each containing a minimum of 1 and a maximum of 64 entries. While one table is in use for the current hopping frame, the other table is loaded and ready for the next hopping frame. Each entry informs the ADRV9002 about the configuration of a particular hopping frame. The frequency hopping table can be indexed at any time by auto-incrementing indexing (starting from the first entry of the first table, to the last entry of the second table, and then back to the first entry of the first table in the case of two hopping tables, or continuously looping in the case of one hopping table), or by a specific entry indicated by a digital GPIO.

Figure 7 shows the frequency hopping tables A and B, each containing N entries (1 ≤ N ≤ 64). Each entry in the table contains four important parameters: hopping frequency, intermediate frequency (only for receive IF mode), index to the receive gain table, and transmit attenuation. In TDD operation, the user must inform the ADRV9002 which channel (transmit or receive) is enabled for each hop frame through dedicated channel setup signals (one for each transmit channel and one for each receive channel). Therefore, although each entry in the frequency hopping table contains both receive and transmit parameters, only the relevant parameters are used.

Figure 7. ADRV9002 frequency hopping table contents and indexing method.

Before we go further into how to use the frequency hopping table in frequency hopping mode, we need to understand the general communication between the ADRV9002 and the baseband integrated circuit (BBIC).

As shown in Figure 8, BBIC, as the main part of the frequency hopping operation, sets the frequency hopping mode, channel setting signals (Rx1_ENBALE, Rx2_ENABLE, Tx1_ENABLE, and Tx2_ENABLE), HOP signals (HOP1 and HOP2), and static or dynamic frequency hopping tables (including hopping frequency, receive IF frequency, index of receive gain table, and transmit attenuation). BBIC communicates with ADRV9002 through SPI interface or DGPIO. ADRV9002, as a node, receives the signal from BBIC and then configures the data path and LO accordingly for frequency hopping.

Figure 8. How the ADRV9002 and BBIC are connected

A rough block diagram of the communication during frequency hopping.

Figure 9 shows an example of a dynamic table where only one frequency is loaded into each frequency hopping table A and B. This is an extreme case that allows the user to change the frequency hopping on the fly for each frame. This example uses the PLL multiplexing mode. As shown in Figure 8, the rising and falling edges of the frequency hopping signal define the timing boundaries of the hopping frame, and as mentioned earlier, each hopping frame consists of a transition time and a dwell time. The rising edge of the channel setting signal defines the hopping frame type after a frame delay (this delay is necessary in PLL multiplexing mode).

Figure 9. In PLL multiplexing mode,

Example of dynamically loading a frequency using the frequency hopping table.

Note that the channel setup signal can represent either a transmit setup signal or a receive setup signal. Figure 9 shows a simplified version of this signal. Since TDD operation involves both transmit and receive, the user needs to configure the transmit setup signal and receive setup signal separately. In addition to indicating the frame hopping type, the channel setup signal can also be used to trigger the BBIC to load the frequency hopping table. The frequency hopping table loading should be completed before the frequency hopping signal edge after the falling edge of the channel setup signal, and then the PLL starts tuning to the frequency on the same frequency hopping signal edge and prepares for the next frame hopping indicated by the next frequency hopping edge. Table A and Table B operate in ping-pong mode, so that after loading, the frequency of one table is used for frequency hopping operation while the frequency of the other table is tuned.

Figure 10 shows the transmit output frequency vs. time when the frequency hopping table is dynamically loaded with 4 and 8 entries each time. The transmit input has 4 frames of 0 kHz, –100 kHz, –200 kHz, and –300 kHz frequencies and is fed to the ADRV9002 by continuously looping through these frames. It is perfectly matched and synchronized with the hopping frames, so the 0 kHz input frame corresponds to the 3.1 GHz LO. During frequency hopping, when the LO changes to the next frequency, the transmit input frequency also changes to the next frequency.

Figure 10. Dynamically loading the frequency hopping table

Comparison of frequency hopping results when 4 items and 8 items are loaded each time.

When frequency hopping is performed, Table A and Table B are dynamically loaded (for simplicity and ease of observation, the table contents do not change each time they are loaded). For each load of 4 items, four consecutive transmit output frames are seen at the 3.1 GHz output frequency, and then four consecutive transmit output frames are seen at the 3.1004 GHz output frequency, and then this pattern repeats. For each load of 8 items, four consecutive transmit output frames are seen at the 3.1 GHz output frequency, four consecutive frames at the 3.1004 GHz output frequency, four consecutive frames at the 3.1008 Hz output frequency, and four consecutive frames at the 3.1012 GHz output frequency, and then this pattern repeats. The transmit output shown in Figure 8 confirms that the dynamic table loading operation is exactly as expected.

As shown in Figure 2, the ADRV9002 supports dual transmit and receive channels. Frequency hopping can be applied to the two channels to achieve channel diversity or channel multiplexing.

To achieve diversity, both channels are frequency hopping simultaneously using the same PLL (one or two), the same frequency hopping table, and TDD timing configuration. The user can enable the MCS feature provided by the ADRV9002 to ensure that multiple channels on the same or different ADRV9002 devices are fully synchronized with each other to guarantee deterministic latency. Phase synchronization can also be achieved through MCS, but this must be performed each time the PLL re-tunes the frequency. MCS allows synchronization of multiple channels during frequency hopping, making the ADRV9002 a very attractive solution for MIMO diversity applications involving frequency hopping. For more detailed information on the requirements and limitations of using MCS during frequency hopping, refer to the ADRV9001 System Development User Guide.

For channel multiplexing, each transmit and receive channel pair uses one PLL to perform frequency hopping independently of each other. One limitation is that very fast frequency hopping (which requires two PLLs for one transmit and receive channel pair) cannot be used to multiplex two pairs of channels in one ADRV9002 device.

In addition to the 2T2R mode, it is also worth mentioning that the ADRV9002 also supports 1T2R and 2T1R frequency hopping operations, thus being able to more flexibly meet the specific requirements of users.

The ADRV9002 also supports DPD operation for both narrowband and wideband applications. It achieves standard-compliant adjacent channel power leakage ratio (ACPR) performance while correcting the nonlinearity of the power amplifier (PA), significantly improving the efficiency of the PA.

An advanced feature of the ADRV9002 is that DPD can be performed in conjunction with frequency hopping. In this case, the ADRV9002 allows the user to configure up to eight frequency regions, and the DPD algorithm creates an optimized solution for each frequency region. For each region, the DPD solution is presented as a set of coefficients that can be stored and loaded at the beginning and end of the transmission, respectively. This ensures that PA linearity is maintained throughout the frequency hopping range.

Since DPD is an adaptive filtering process, a set of samples must be captured periodically for coefficient calculation, so the frame skipping length needs to be long enough to meet the DPD capture length requirement. However, if the user only uses the initially loaded DPD coefficients and does not need to perform DPD updates, there is no such limitation.

Tracking calibration of the ADRV9002 is not typically performed during rapid frequency hopping. However, an initial calibration is performed over multiple frequency regions to achieve optimal performance, depending on the user's frequency hopping configuration.

The ADRV9002 TES software allows users to fully test the frequency hopping performance on the evaluation board. TES supports the Xilinx ^® ZC706 and ZCU102 FPGA evaluation boards. As shown in Figure 11, the frequency hopping configuration page can be easily used to configure the frequency hopping parameters, including the frequency hopping operation mode, frequency hopping table, GPIO settings, and TDD timing. TES has built-in FPGA synchronization function, so users can accurately control the TDD timing to ensure that the transmission or reception of the frame can be fully synchronized with the hopping frame. Many frequency hopping examples are also provided in TES for users to further analyze and study.

Figure 11. Configuring frequency hopping via TES.

Frequency hopping is one of the advanced system features of the next generation SDR transceiver ADRV9002. ADRV9002 uses two PLLs, multiple frequency hopping modes, and flexible methods of loading and indexing frequency hopping tables to provide users with excellent frequency hopping capabilities to cope with various applications and meet higher system requirements. All functions can be fully evaluated through the ADRV9002 TES and software development kit (SDK).