Here is a way to simplify FPGA power system management~

FPGAs are rapidly gaining ground and are being widely deployed at scale. For example, after successfully using FPGAs to speed up the Bing search engine in a 2013 pilot project, Microsoft ^® expanded the use of FPGA-equipped servers to its cloud data centers.

FPGAs require several different low-voltage supply rails, each with its own voltage and current specifications, to power their core logic, I/O circuits, auxiliary logic, transceivers, and memory. These rails may need to be turned on and off in a specific order to avoid damaging the FPGA. Point-of-load (POL) regulators step down the higher input supply voltage of the board to the multiple input voltages required by the FPGA. When power conversion efficiency is critical, switching regulators are used as POL regulators, while linear regulators, such as low dropout (LDO) regulators, are used for noise-sensitive circuits such as PLLs and transceivers.

Typical board input voltages are 5 V, 12 V, 24 V, and 48 V, while the input voltage range for FPGAs is less than 1 V to about 3 V. For high input voltages (12 V, 24 V, 48 V), additional buck regulators may be required to generate intermediate bus voltages that feed the POL regulators (see Figure 1). Among the FPGA power rails, the core voltage requires the lowest voltage (about equal to or less than 1 V) and the highest accuracy (±3% or better), with current levels of tens of amps, depending on the utilization of the FPGA resources. To prevent logic errors, voltage fluctuations need to be controlled within tens of millivolts as required by the FPGA power rail tolerance specifications not only under DC conditions but also during FPGA current transients. The worse the DC accuracy of the power supply, the more bypass capacitors are required to maintain a usable supply voltage under transient conditions. For example, assume a ±3% core voltage tolerance specification. When using a DC power supply with an accuracy of ±1%, the corresponding transient tolerance is ±2%. When the DC power supply has a lower accuracy (±2%), the transient tolerance will be tighter (±1%), requiring more bypass capacitors than in the previous example.

Adjusting or fine-tuning the FPGA supply voltage level from a default set point is necessary when making final design changes, reusing a design in another application, performing board margin testing, and dynamically optimizing system power consumption during development or field operation. In this case, using multiple different resistors in parallel in the power supply feedback network is not the fastest or most feasible solution. One way to implement voltage fine-tuning is to use a digital-to-analog converter (DAC) to drive the regulator's feedback network (see Figure 2). Software code needs to be written for the fine-tuning routine to obtain supply voltage measurement data from the analog-to-digital converter (ADC) to calculate the correct DAC code, and then slowly adjust the DAC output to the calculated digital code, gradually and steadily increasing the supply voltage to reach the target voltage level without glitches or overshoot. This fine-tuning routine needs to be repeated to ensure that the power supply does not deviate from the target voltage due to component drift over time or temperature changes.

Monitoring FPGA supply voltage, current, and fault conditions is critical to understanding the health and power consumption of the system under different scenarios, because the FPGA is the core of the entire electronic system. Combining this understanding with fine-tuning capabilities can avoid designing the power supply for the worst case, saving cost and power. In addition, potential system failures may manifest as abnormal FPGA power consumption, allowing the host controller or maintenance personnel to detect the problem early before the board or system fails. Voltage monitoring requires the use of an ADC, while current monitoring also requires the use of a level shift circuit to convert the high-level current sense voltage to a ground reference voltage; for example, as shown in Figure 3, by using a transconductance amplifier.

Although we haven't discussed fault management yet, this long list of requirements may already make your head spin. What happens when a POL output experiences an undervoltage or overvoltage, that is, outside of the valid voltage window? Should only the faulty supply be shut down? Or should other supplies be shut down as well? How do you eliminate a fault that causes the system board to shut down?

As we can see, power system management for FPGAs can quickly become very complex, distracting from the basic FPGA application. Note that the FPGA's power tree is only part of the overall power system on a digital processing board. Most of the above requirements also apply to other digital devices such as ASICs, DSPs, GPUs, SoCs, and microprocessors. What is needed is a simple, scalable, and flexible power system management solution.

Analog Devices offers a portfolio of digital power system management (DPSM) devices to meet the complex power system requirements found in digital processing boards. DPSM devices are available with or without integrated DC/DC conversion to replace POL regulators or to work with existing POL regulators. Power system managers do not provide DC/DC conversion and add digital monitoring and control capabilities to existing analog power systems consisting of switching or LDO regulators. Using a single device, such as the LTC2980, 16 POL regulators can be trimmed, margined, monitored, sequenced, powered, fault logged, and managed. Devices with different channel counts (2, 4, 8, or 16 channels) can be mixed and matched to manage hundreds of power rails. The dual-channel LTC2972 is the latest addition to the family and provides an easy to get started solution to monitor and control the two most important rails in such a power system; for example, the FPGA core rail and the auxiliary rail.

The LTC2972 is a dual-channel power system manager that adds comprehensive software-based monitoring, control, and black-box fault logging to FPGA, ASIC, and processor boards, accelerating time to market, improving system reliability, and optimizing board power consumption (Figure 4). POL power supply output voltages are fine-tuned, margined, and monitored using an outstanding 16-bit ADC with a total unadjusted error (TUE) of 0.25% to improve board power and long-term performance. Because the POL output voltage can be tightly controlled to ±0.25% accuracy, there is plenty of headroom during load transients (±2.75% accuracy at ±3% FPGA rail specifications), significantly reducing the required bypass capacitors and freeing up board space. The power supply output current is measured using a sense resistor, inductor DCR, or the IMON output of the power supply. The voltage and current measurements are multiplied internally to provide a POL output power reading.

The LTC2972 has built-in power sequencing, monitoring, and EEPROM fault logging. Sequencing is accomplished by writing time delays to internal registers or using cascaded power-good signals. Dedicated fast comparators signal faults when POL input voltage, output voltage, and temperature digitally deviate from settable upper and lower thresholds. Faults trigger EEPROM black box logging, simplifying fault analysis and providing relevant insights for future system improvements. The first fault command provides more information about the cause of the system failure. Fault information can be flexibly propagated to other supplies or other DPSM devices.

The LTC2972 supports voltage, current, power and energy monitoring of the intermediate bus input of the POL converter. In order to manage, optimize and reduce board power consumption, thereby reducing cooling and utility costs in servers and data centers, it is necessary to monitor board power and energy usage. The LTC2972 conveniently provides output energy (in joules) and operating time through the PMBus interface (an industry standard for communicating with power management and conversion devices) to reduce heavy polling and calculation tasks. Combining the LTC2972 with digital measurements of POL output voltage, current and power, the conversion efficiency of the power system can be monitored over a long period of time.

Each channel is equipped with a programmable power good pin or general purpose input/output (GPIO) pin. The LTC2972 interfaces with other power system managers to enable sequencing and fault management of more than two power rails. Flexible programming and data readback of the power system are possible using compatible PMBus commands transmitted over the I ^{2 C/SMBus interface. Configuration is done in the LTpowerPlay ®} development environment that supports all ADI DPSM products (see Figure 5). Once the internal EEPROM is programmed with the desired application-specific configuration, there is no need to write software code for automatic operation.

FPGAs are widely used in various electronic systems, even replacing ASICs, but they have complex power systems around them. Analog Devices offers a variety of DPSM products to help simplify power system management. If you have never used DPSM before, you can try the LTC2972, an entry-level product that can solve complex power system problems on digital processing circuit boards.