This time, let's delve into the accuracy and bandwidth issues of ADC~

Generally speaking, the internal front end of an ADC needs to settle within half a cycle or sampling clock period (0.5/Fs) to provide an accurate representation of the analog signal captured internally. Therefore, for a 12-bit ADC (sampling rate of 2.5 GSPS, full-scale input range of 1.3 V pp), the full power bandwidth (FPBW) can be derived from the following transient formula:

Solving for t:

Substituting in τ = 1/(2 × π × FPBW), a time constant, we solve for FPBW:

Now, let t = 0.5/Fs. The time required for the sample to settle is as follows (the sample period is 1/Fs):

This minimizes the bandwidth or FPBW required by the internal front end of the ADC. This is the bandwidth required for the internal front end of the converter to settle to within 1 LSB and correctly sample the analog signal. This will take several time constants to meet the 1 LSB accuracy requirement of this type of ADC.

One time constant is 24 ps or τ = 1/(2 × π × FPBW). To understand the number of time constants required to achieve the LSB size requirement over the full-scale range of the ADC, we need to find the full-scale error or %FS.

Or 1 LSB = FS/(2N), where N = the number of bits;

Or 1.3 V pp/(212) = 317 mV pp, and %FS = (LSB/FS) × 100 = 0.0244.

By plotting the Euler number, or eτ, a curve can be drawn so that the relative error can be easily seen at each time constant. As can be seen in Figure 1, it takes 8.4 time constants for a 12-bit ADC sample to settle to within approximately 1 LSB.

Figure 1. Settling accuracy vs. time constant

This allows the designer to estimate the maximum analog input frequency or sampling bandwidth that can be used for the converter and still settle to within 1 LSB error. Outside this range, the ADC cannot accurately represent the signal. This can be simply defined as:

FMAX = 1/(τ × number of time constants)

or

1/(24 ps × 8.4) = 4.96 GHz

Keep in mind that this represents a best-case scenario and assumes a single-pole ADC front end. Not all real-world converters will work this way, but it is a good start.

The ADC full power bandwidth is different from the defined usable bandwidth or sampling bandwidth of the converter. It can be thought of as the full power bandwidth (FPBW) of the analog signal input to the operational amplifier, the signal is more like a triangle wave signal, and there is a lot of distortion at the output.

The FPBW is the bandwidth required for the ADC to accurately capture the signal and for the internal front end to settle correctly (6.62 GHz in the previous example). It is not a good idea to choose an IF and use the converter within that range because the performance results of the system will change significantly; at about 5 GHz, the full-scale bandwidth is much higher than the maximum sampling bandwidth of the converter itself, based on the rated resolution and performance specifications in the converter data sheet.

Designs revolve around sampling bandwidth. All designs should avoid using some or all of the highest frequency portions of the rated full-power bandwidth, otherwise the dynamic performance (SNR/SFDR) will degrade and change significantly. To determine the sampling bandwidth of a high speed ADC, the examples in this article should be used, as these data are not always available in the data sheet.

Typically, data sheets specify or even list the frequencies within the converter’s sampling bandwidth that are production tested and guarantee the specified performance. However, in older ADC products these test frequencies are not always defined in the data sheet as FMAX. There needs to be better specification, definition, and testing of these bandwidth terms in the industry going forward.