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FPGA Implementation of High-Speed ​​Floating-Point FFT Processor

  • 2013-07-01
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Abstract: This paper introduces the design of a 1024-point custom 24-bit floating-point FFT processor based on FPGA. The improved butterfly operation unit is used to reduce the hardware consumption of the system and improve the system performance. The pipelining method is used to improve the processing speed of the system, so that the calculation and memory read/write operations are coordinated; the floating-point algorithm makes the system have higher processing accuracy. This design method can be widely used in the field of high-speed digital signal processing. [Author Abstract]

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