Abstract: Aiming at the characteristics of the video input signal in VGA format, a signal controller suitable for LCOS field sequential color display is designed in combination with complex programmable logic device (CPLD). With CPLD as the core, the ping-pong operation idea is adopted to coordinate the reading and writing of signals between two external static random access memories (SRAM), and the data is converted from serial to parallel, and the parallel input red, green, and blue video data are converted into red, green, and blue sub-field data, thereby realizing field sequential color display. The design adopts the technology of reducing the refresh frequency to reduce the system power consumption. Finally, the EDA tool is used for comprehensive simulation. [Author Abstract]
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