With the increasing complexity of SoC architecture design, the traditional bus structure has become a bottleneck for communication between IP cores. In order to meet the needs of large-scale integrated circuit development in terms of scalability, energy consumption, area, clock asynchrony, reusability, QoS, etc., a new design method - network on chip (NoC) came into being, which is an innovation of the original design model. This paper analyzes the technical characteristics of NoC and the key technologies in this field, classifies the common topologies in NoC in detail, and points out the advantages and disadvantages of each topology; then, by analyzing the performance parameters of each topology, a comprehensive comparison of their performance is made. Keywords: network on chip, grid, topology
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