4-bit D register (3S, Q output) 54173/7417354LS173/74LS173170 is a 4-bit register with three-state output, with two line structures: 54/74173 and 54LS173/74LS173. The typical values of its main electrical characteristics are as follows: Model fm PD54170/74170 35MHz 250mW54LS170/74LS170 50MHz 95mW173\'s output (Q) can be directly connected to the bus. When the three-state enable control terminals (ENA, ENB) are both low, the output terminals (1Q~4Q) are in normal logic state and can be used to drive the load or bus. When A EN or B EN is high, 1Q~4Q are in high impedance state, neither driving the bus nor being the load of the bus, but the timing operation of the trigger is not affected. The data strobe terminal (A ST, B ST) can control the data (1D~4D) to enter the trigger. When the data strobe terminals (A ST, B ST) are both low level, under the rising edge of the clock (CP) pulse, 1D~4D enter the corresponding trigger. Terminal Symbol CP Clock Input Terminal (Rising Edge Valid) CR Clear Terminal 1D~4D Data Input Terminal A EN, B EN Tri-state Enable Terminal (Low Level Valid) 1Q~4Q Output Terminal A ST, B ST Data Strobe Terminal (Low Level Valid)
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