Tokyo, September 19, 2007 - Renesas Technology Corp. announced that it has developed a new filter circuit technology that enables the integration of discrete-time filters*1 with small circuit area and low power consumption on multimode communication RF transceiver ICs supporting a variety of wireless systems. This technology is a circuit technology that helps reduce the number of capacitors used in discrete-time filters, eliminating approximately half of the capacitors compared to current technology. Trial fabrication using a 130nm (nanometer) CMOS process using these technologies has demonstrated the world\'s lowest levels of circuit area and power consumption, with a filter core circuit area of only 1.8mm2 and current consumption of only 11mA at a 1.5V power supply voltage. It has also demonstrated the realization of the rejection characteristics required for GSM*2, W-CDMA*3 and wireless LAN (local area network) communication systems. Renesas Technology will present these results at the 2007 Custom Integrated Circuit Conference (CICC) to be held in San Jose, California on September 16, 2007.
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