Design of a method to eliminate the metastable state of asynchronous timing

2013-09-22
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A FIFO is proposed that generates empty and full flags based on asynchronous comparison method and uses latches to synchronize flags with clocks. The corresponding Verilog HDL code is also given. This method can increase clock frequency and save layout area.

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Design of a method to eliminate the metastable state of asynchronous timing

Document Introduction