This paper introduces a method of using FPGA devices to complete high-speed digital transmission. This method is used to realize the high-speed data interface of wireless transceiver chip nRF2401A. To further improve the transmission rate, the transmitted data is also compressed in the designed interface system. The high speed data interface and the corresponding data compressing algorithm are programmed using VHDL. The whole system has been tested, which shows the feasibility of the designing method based on FPGA.Keywords: FPGA , digital transmission, digital compression, digital radio
You Might Like
Recommended ContentMore
Open source project More
Popular Components
Searched by Users
Just Take a LookMore
Trending Downloads
Trending ArticlesMore