ppt

Digital Correction Technology for 1.5-bit/stage Pipeline ADC

  • 2020-12-02
  • 1.48MB
  • Points it Requires : 1

According to the digital correction principle introduced above, we adopt a simplified digital correction method. The specific algorithm of this correction method is: 1) The comparison result of each level is sent to the cache unit. After a pipeline cycle is completed, the results of each level output after the encoder (recorded as di1di0, i is the i-th level, di1 is the high bit) are sent to the digital correction circuit at the same time. 2) Calculate according to the following formula, that is, realize the staggered addition of the results from the first level to the last level.

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