As shown in the following figure, the left side is the read timing diagram of STM32 FSMC mode A, and the right side is the read timing diagram of SRAM. From the figure, STM32 can only set the tRC time
2812 has a three-level interrupt mechanism, namely the peripheral level, PIE level and CPU level. For a specific peripheral interrupt request, if any level is not allowed, the CPU will not execute the