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Optimal Design and Implementation of High-Rate LDPC Code Decoder

2013-09-22
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This paper takes the 7/8 code rate LDPC code recommended by CCSDS as an example and proposes a hardware structure optimization method suitable for high code rate LDPC code decoder. High code rate LDPC codes are usually accompanied by the problem of high ratio of row weight to column weight. This method optimizes the commonly used partial parallel decoding structure on the basis of splitting the check matrix, reduces the complexity imbalance between the check node operation unit (CNU) and the variable node operation unit (VNU) when decoding high code rate LDPC codes, and thus improves the clock performance of the decoder. Experiments show that the structure provided by this scheme saves 41% of hardware resources compared with the commonly used partial parallel decoding structure; the code rate of the partial parallel decoding scheme using the same hardware resources as the scheme in this paper without matrix splitting is 75% of that of the scheme in this paper.

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