Research and design a high-performance radix-4 fast Fourier transform (FFT) processor. The radix-4 algorithm and pipelined butterfly operation unit are used to improve the processing speed and enable the chip to operate at a higher clock frequency. The overflow detection state machine is used to perform block floating-point checks on the data output by each butterfly operation unit to ensure correct judgment of overflow conditions. Verification and performance evaluation results show that the FFT processor has high performance. Keywords: Fast Fourier transform algorithm; Radix-4 algorithm; Block floating-point algorithm; Butterfly operation unit
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