ESD is a common occurrence that affects all handheld devices. ICs must be protected because most cannot withstand ESD above 2 kV. ON Semiconductor\'s ESD protection devices clamp the 8 kilovolt (kV) pulse of the IEC 61000-4-2 ESD suppression standard with the fastest response time and lowest clamping voltage. In the past, ESD did not seem to be a problem because electronic devices were not as small and the IC devices used were much larger than they are today. Because larger devices have greater capacitance, they can hold more charge per volt (V) and are therefore less sensitive to ESD than smaller devices. However, as electronic devices become smaller, more functional, and more sophisticated, using semiconductor processes below submicron, IC designs are more sensitive to ESD and more susceptible to ESD damage, making ESD a design challenge. Designers must make ICs provide the most effective ESD protection possible while reducing board space for additional protection components. The input/output connectors of electronic circuits provide a path for ESD to enter. Taking a mobile phone as an example, the volume button, voice button, smart button, charger jack, accessory connection port, speaker, keypad, amplifier, SIM card, battery connector, etc. may become the entry point of ESD, making it easy to reach the circuit and voltage-sensitive components. When the incoming ESD voltage is high enough, an arc will be generated on the dielectric of the IC device, burning microscopic holes in the gate oxide layer, causing permanent damage to the device. Separation of ESD protection from CMOS chips People have tried to integrate ESD protection with CMOS chips, which is not impossible. However, with the transfer of semiconductor processes to below 65 nm, the area of ESD protection, which originally occupied only a few tenths of the chip area of 1.5 μm process (to obtain 2 kV ESD protection), can no longer be accommodated in the current chip of only a few nanometers. Under the 65 nm process, the area of ESD protection even exceeds the area of the entire chip. On the contrary, the more sophisticated the process, the higher the requirement for ESD protection. Therefore, effective ESD protection can no longer be fully integrated into the CMOS chip. In addition, for electronic devices, external protection devices can more effectively prevent ESD from easily entering circuits and voltage-sensitive components. The mandatory ESD suppression standard IEC61000-4-2 requires that protection devices should be placed at connectors or ports to effectively suppress the occurrence of ESD events before ESD enters the circuit board. Comparison between TVS and varistors Traditionally, electronic equipment manufacturers use varistors for ESD protection, but they have the disadvantages of large size and poor performance. In terms of packaging, compared with the 0402 multilayer varistors, the recommended soldering area of ON Semiconductor\'s ultra-micro ESD devices is 0.54 mm2 for SOD-923 TVS, 0.7 mm2 for SOD-723 TVS, and 0.9 mm2 for 0402 varistors. In terms of cross-sectional height, SOD-923 TVS is 0.4 mm, SOD-723 TVS is 0.5 mm, and 0402 varistors are 0.9 mm. More importantly, the performance of TVS and varistors is incomparable. ON Semiconductor\'s ESD devices have better clamping performance, lower leakage and longer service life. Using a high-frequency test circuit board to provide ESD contact discharge pulse current and an ESD gun to test the performance of ESD protection devices, the real clamping voltage curve shown in Figure 1 can be seen on the oscilloscope. The TVS device can immediately suppress the incoming voltage to a very low level, quickly clamping from 8 kV static electricity to 5-6 V; but the curve of the varistor drops very slowly and cannot drop to a very low level. The curve shows that the recovery time of the TVS device is very short, and the energy leaked to the subsequent circuit through the TVS device is also very small. For portable devices, the less energy entering, the better.
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