With the increase of ADC device speed and the improvement of FPGA and DSP device operation speed, high-speed and stable data transmission is required between high-speed AD and signal processing system. The bandwidth of CPCI and FDPD high-speed buses, which were widely used before, can no longer meet the data transmission rate requirements of broadband receivers, becoming a new bottleneck affecting receiver performance. In view of this situation, a DDR transmission interface based on LVDS differential interface is proposed to solve this bottleneck, and FPGA is implemented on the actual hardware platform, reaching an interface rate of 18.4 Gbit/s.
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