A new highly balanced and highly reliable front-end controllable clock tree design method is proposed to solve the problem that the clock tree needs to be repeated many times in the back-end tool to meet the performance and power consumption requirements. It explains how to solve the problems often encountered in clock tree design from two aspects: front-end optimization and back-end constraints. On this basis, the front-end and back-end methods are combined to complete the clock tree design. The results verify that this method can reduce power consumption by about 20% and save design time. This method can be widely used in clock-based synchronous digital circuit design. Keywords: clock tree; balance; collaborative design; back-end
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