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ADSP-TS101S Chinese data pdf

  • 2013-09-22
  • 1.09MB
  • Points it Requires : 2

Main performance 300MHz running speed, 3.3ns instruction cycle 6M Bits on-chip SRAM 19×19mm (484-Ball) or 27×27mm (625-Ball) PGBA package Dual operation modules - each contains an ALU, a multiplier, a shifter and a register group Dual integer ALU, providing data addressing and pointer operation functions Integrated I/O including 14-channel DMA controller, external port, 4 link ports, SDRAM controller, programmable flag pin, 2 timers and timer full pin, etc. For system IEEE 1149.1 compatible JTAG port for on-chip emulation On-chip arbitration Up to 8 TigerSHARC can be seamlessly connected through a shared bus DSP main advantages Provide high-performance static superscalar DSP operations, specially optimized for communications and large applications requiring multiple DSP processors Outstanding DSP algorithm and I/O performance (see Table 1 and Table 2 for I/O performance) DMA controller supports 14 DMA channels, which can complete low-overhead transfers between on-chip memory, off-chip memory, memory-mapped peripherals, link ports, host processors and other (multi-processor) DSPs Very flexible instruction set and DSP structure supporting friendly high-level languages ​​Facilitates DSP programming Scalable multi-processor system with only low communication overhead

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