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A low-power 32-bit multiplier based on a skip-type Wallace tree

2013-09-22
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In order to improve the comprehensive performance of the multiplier, the multiplier was optimized from three aspects. The improved Booth algorithm was used to generate each partial product, the skipping Wallace tree structure was used to compress the partial products, and the compressed results were summed by the improved LING adder. The design was verified and tested on FPGA, and logic synthesis and layout and routing were performed under 0.18 μm SMIC process. The results show that compared with the multiplier using the traditional Wallace tree structure, the delay of the multiplier is reduced by 29%, the area is reduced by 17%, and the power consumption is reduced by 38%, which can meet the high-performance processing requirements. Keywords: Booth algorithm; skipping Wallace tree; multiplier; LING adder

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