With the increase of clock frequency, bus bandwidth and speed, the influence of interconnection system on the whole system is getting bigger and bigger, and in some cases it has become the most important factor in determining system performance. In the future, this trend will be more obvious, and to some extent, the design of interconnection system will dominate the electrical design of the system. The continuous increase of system clock frequency makes the timing budget of interconnection system decrease exponentially. At present, the timing budget has been reduced to the order of 1Jps, so once the interconnection system has an error, it will affect the timing of the whole system and cause system data transmission errors.
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