Design of 120MHz High-speed A/D Acquisition Card Based on CPLD Fadong Xu Zhengjun Zhai High-speed A/D acquisition technology has been increasingly widely used in many fields. This article will discuss in detail the design method of using CPLD technology to implement a 120MHz high-speed A/D acquisition card. The acquisition card has multiple triggering modes including negative delay triggering. It is implemented using CPLD complex programmable logic device (also known as FPGA) EPM7128SQC100-7 and AD\'s high-speed analog-to-digital converter (A/D) AD9054BST-135. EPM7128SQC100-7 contains 128 macro units (or 2500 available gates), and its pin-to-pin shortest transmission delay is 7ns. It uses a single +5V power supply, can be programmed online through the JTAG interface, and has 84 I/O pins available for users (4 of which are dedicated input pins). The device uses PQFP-100 package. Among them, TDI, TDO, TMS, and TCLK are programming pins; GCLK, GOE, GCLEAR, and REDIN are dedicated input pins; VCCINT and VCCIO are connected to +5V power supply; GND is grounded; I/O is user programmable input and output pin. When the I/O pin is used as output, it can be set by the user to three states: 0, 1, and Z.
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