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Design of high-speed, high-order FIR filter based on FPGA

  • 2013-07-01
  • 99.58KB
  • Points it Requires : 2

Abstract: Based on the LUT structure of FPGA, an improved DA algorithm is proposed to realize high-speed and high-order FIR filter in time domain to meet the needs of radar digital pulse compression. It is experimentally verified on Xilinx\'s VertexⅡ FPGA.

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