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An Optimized Design of DDS Phase Accumulator Based on Verilog_HDL

  • 2013-07-01
  • 180.8KB
  • Points it Requires : 1

Abstract: Through the comparative analysis of the traditional design methods of DDS phase accumulator based on Verilog HDL, a scheme of designing phase accumulator by combining pipeline technology adder with register is proposed. This scheme has the advantages of improving speed and saving resources. Taking an eight-bit phase accumulator as an example, the experimental simulation results are given.

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