Abstract: Through the comparative analysis of the traditional design methods of DDS phase accumulator based on Verilog HDL, a scheme of designing phase accumulator by combining pipeline technology adder with register is proposed. This scheme has the advantages of improving speed and saving resources. Taking an eight-bit phase accumulator as an example, the experimental simulation results are given.
You Might Like
Recommended ContentMore
Open source project More
Popular Components
Searched by Users
Just Take a LookMore
Trending Downloads
Trending ArticlesMore