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Semiconductor
MSM27V3255CZ
1,048,576-Double Word x 32-Bit or 2,097,152-Word x 16-Bit
4-Double Word x 32-Bit or 8-Word x 16-Bit Page Mode One Time PROM
DESCRIPTION
1A
The MSM27V3255CZ is a 32Mbit electrically Programmable Read-Only Memory with page mode. Its
configuration can be electrically switched between 1,048,576 double word x 32bit and 2,097,152
word x 16bit. The MSM27V3255CZ operates on a single +3.3V power supply and is TTL compatible.
The MSM27V3255CZ provides Page mode which can greatly reduce the read access time. Since the
MSM27V3255CZ operates asynchronously , external clocks are not required , making this device
easy-to-use. The MSM27V3255CZ is suitable as large-capacity fixed memory for microcomputers
and data terminals. It is manufactured using a CMOS double silicon gate technology and is offered in
70-pin SSOP package.
FEATURES
• 1,048,576 double word x 32bit / 2,097,152 word x 16bit electrically switchable configuration
• Single +3.3V power supply
• Access time 100ns
Page mode access time 30ns
• Input / Output TTL compatible
• Three-state output
• Packages
70-pin plastic SSOP (SSOP70-P-500-0.80-K)
October 1998
1
MSM27V3255CZ
PIN CONFIGURATION (TOP VIEW)
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
V
CC
7
D0 8
D16 9
D1 10
D17 11
V
SS
12
V
CC
13
D2 14
D18 15
D3 16
D19 17
D4 18
D20 19
D5 20
D21 21
V
SS
22
V
CC
23
D6 24
D22 25
D7 26
D23 27
V
SS
28
A6 29
A7 30
A8 31
A9 32
A10 33
A11 34
A12 35
70 V
PP
69 NC
68 NC
67 WORD
66 OE
65 CE
64 V
SS
63 D31/A-1
62 D15
61 D30
60 D14
59 V
SS
58 V
CC
57 D29
56 D13
55 D28
54 D12
53 D27
52 D11
51 D26
50 D10
49 V
SS
48 V
CC
47 D25
46 D9
45 D24
44 D8
43 V
CC
42 A19
41 A18
40 A17
39 A16
38 A15
37 A14
36 A13
PIN NAMES
D31/A-1
A0 - A19
D0 - D30
CE
OE
V
CC
V
SS
WORD
V
PP
NC
FUNCTIONS
Data output / Address input
Address input
Data output
Chip enable
Output enable
Power supply voltage
GND
Mode switch
Program power supply voltage
Non connection
70-pin SSOP
2
MSM27V3255CZ
BLOCK DIAGRAM
A-1
X16/X32 Switch
CE
OE
WORD
CE
OE
PGM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
Row Decoder
Memory Matrix
Address Buffer
1,048,576X32-Bit or 2,097,152X16-Bit
Column Decoder
Multiplexer & Page Data Latch
Output Buffer
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D30
D10
D11
D12
D13
D14
D15
In 16-bit output mode, these pins are
three-stated and pin D31 functions
as the A-1 address pin.
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D31
FUNCTION TABLE
MODE
READ (32-Bit)
READ (16-Bit)
OUTPUT DISABLE
STAND-BY
PROGRAM
PROGRAM INHIBIT
PROGRAM VERIFY
* : Don't Care
CE
L
L
L
H
L
H
H
OE
L
L
H
*
H
H
L
L
11.0V
5.0V
D
OUT
WORD
H
L
H
L
H
L
D
IN
*
3.3V
D
OUT
V
PP
V
CC
D0 - D15
D16 - D30
D
OUT
Hi-Z
Hi-Z
*
Hi-Z
Hi-Z
Hi-Z
Hi-Z
L/H
*
L/H
D31/A-1
L/H
3
MSM27V3255CZ
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating temperature under bias
Storage temperature
Input voltage
Output voltage
Power supply voltage
Program power supply voltage
Power dissipation per package
Symbol
Topr
T
stg
V
I
V
O
V
CC
V
PP
P
D
-
relative to V
SS
Condition
-
Value
0 to 70
-55 to 125
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
-0.5 to 7
-0.5 to 12.5
1.0
Unit
°C
°C
V
V
V
V
W
RECOMMENDED OPERATING CONDITIONS FOR READ
(Ta=0 to 70
°C)
Parameter
V
CC
power supply voltage
V
PP
power supply voltage
Input "H" level
Input "L" level
Voltage is relative to Vss
Symbol
V
CC
V
PP
V
IH
V
IL
V
CC
=3.0V-3.6V
Condition
Min.
3.0
-0.5
2.2
-0.5
Typ.
-
-
-
-
Max.
3.6
V
CC
+0.5
V
CC
+0.5
0.6
Unit
V
V
V
V
4
MSM27V3255CZ
ELECTRICAL CHARACTERISTICS (Read operation)
DC Characteristics
Parameter
Input leakage current
Output leakage current
V
CC
power supply current
(Standby)
V
CC
power supply current
(Read)
V
PP
power supply current
Input "H" level
Input "L" level
Output "H" level
Output "L" level
Voltage is relative to Vss
AC Characteristics
(V
CC
=3.3V
±
0.3V, Ta=0 to 70°C)
Parameter
Address access cycle time
Address access time
Page set up time
Page access cycle time
Page access time
CE access time
OE access time
Output disable time
Output hold time
Symbol
T
C
T
ACC
T
PSET
T
PC
T
PAC
T
CE
T
OE
T
CHZ
T
OHZ
T
OH
Condition
-
CE=OE=V
IL
NOTE(1)
-
-
OE=V
IL
CE=V
IL
OE=V
IL
CE=V
IL
CE=OE=V
IL
Min.
100
-
120
30
-
-
-
0
0
0
Max.
-
100
-
-
30
100
30
30
25
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
I
LI
I
LO
I
CS1
I
CS2
I
CCA
I
PP
V
IH
V
IL
V
OH
V
OL
Condition
V
I
=0 to Vcc
V
O
=0 to Vcc
CE=V
CC
CE=V
IH
CE=V
IL ,
OE=V
IH
tc=100ns
V
PP
=V
CC
-
-
I
OH
=-400µA
I
OL
=2.1mA
(V
CC
=3.3V
±
0.3V, Ta=0 to 70
°
C)
Min.
-
-
-
-
-
-
2.2
-0.5
2.4
-
Typ.
-
-
-
-
-
-
-
-
-
Max.
10
10
50
1
80
10
V
CC
+0.5
0.6
-
0.45
Unit
µA
µA
µA
mA
mA
µA
V
V
V
V
NOTE(1) T
PSET
is defined as the end of either CE trailing edge or address transition in random access
term until the first page address transition.
Measurement conditions
Input signal level
Input timing reference level
Output load
Output timing reference level
0V/3V
0.8V/2.0V
100pF
0.8V/2.0V
1.5V
400ohms
Output
100pF (including jig capacitance)
5
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