EPM7256E datasheet, PDF - EEWORLD Datasheet

EPM7256E: DescriptionEE PLD, 7.5 ns, PQCC84; Categorysemiconductor Programmable logic devices; File Size451KB，62 Pages; ManufacturerAltera (Intel)

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EPM7256E Overview

EE PLD, 7.5 ns, PQCC84

Parameter Name	Attribute value
Number of input and output buses	64
Number of terminals	84
Minimum operating temperature	0.0 Cel
Maximum operating temperature	70 Cel
Processing package description	PLASTIC, LCC-84
each_compli	Yes
state	NRFND
Programmable logic type	EE PLD
clock_frequency_max	167 MHz
in_system_programmable	YES
jesd_30_code	S-PQCC-J84
jesd_609_code	e0
jtag_bs	YES
moisture_sensitivity_level	2
Dedicated input quantity	0.0
umber_of_macro_cells	160
organize	0 DEDICATED INPUTS, 64 I/O
Output function	MACROCELL
Packaging Materials	PLASTIC/EPOXY
ckage_code	QCCJ
ckage_equivalence_code	LDCC84,1.2SQ
packaging shape	SQUARE
Package Size	CHIP CARRIER
eak_reflow_temperature__cel_	220
wer_supplies	3.3/5,5
gation_delay	7.5 ns
qualification_status	COMMERCIAL
seated_height_max	5.08 mm
sub_category	Programmable Logic Devices
Rated supply voltage	5 V
Minimum supply voltage	4.75 V
Maximum supply voltage	5.25 V
surface mount	YES
Craftsmanship	CMOS
Temperature level	COMMERCIAL
terminal coating	TIN LEAD
Terminal form	J BEND
Terminal spacing	1.27 mm
Terminal location	QUAD
ime_peak_reflow_temperature_max__s_	30
length	29.31 mm
width	29.31 mm
dditional_feature	CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V

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