MWS5101AEL3X datasheet, PDF - EEWORLD Datasheet

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MWS5101AEL3X: Description256X4 STANDARD SRAM, 350ns, PDIP22, PLASTIC, DIP-22; Categorystorage storage; File Size43KB，7 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

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256X4 STANDARD SRAM, 350ns, PDIP22, PLASTIC, DIP-22

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MWS5101,

MWS5101A

March 1997

256-Word x 4-Bit

LSI Static RAM

Description

The MWS5101 and MWS5101A are 256 word by 4-bit static

random access memories designed for use in memory

systems where high speed, very low operating current, and

simplicity in use are desirable. They have separate data

inputs and outputs and utilize a single power supply of 4V to

6.5V. The MWS5101 and MWS5101A differ in input voltage

characteristics (MWS5101A is TTL compatible).

Two Chip Select inputs are provided to simplify system

expansion. An Output Disable control provides Wire-OR

capability and is also useful in common Input/Output

systems by forcing the output into a high impedance state

during a write operation independent of the Chip Select input

condition. The output assumes a high impedance state

when the Output Disable is at high level or when the chip is

deselected by CS1 and/or CS2.

The high noise immunity of the CMOS technology is

preserved in this design. For TTL interfacing at 5V operation,

excellent system noise margin is preserved by using an

external pull-up resistor at each input.

For applications requiring wider temperature and operating

voltage ranges, the mechanically and functionally equivalent

static RAM, CDP1822 may be used.

The MWS5101 and MWS5101A types are supplied in 22

lead hermetic dual-in-line, sidebrazed ceramic packages (D

sufﬁx), in 22 lead dual-in-line plastic packages (E sufﬁx), and

in chip form (H sufﬁx).

Features

• Industry Standard Pinout

• Very Low Operating Current . . . . . . . . . . . . . . . . . . 8mA

at V

= 5V and Cycle Time = 1µs

• Two Chip Select Inputs Simple Memory Expansion

• Memory Retention for Standby. . . . . . . . . . . . . 2V (Min)

Battery Voltage

• Output Disable for Common I/O Systems

• Three-State Data Output for Bus Oriented Systems

• Separate Data Inputs and Outputs

• TTL Compatible (MWS5101A)

Pinout

MWS5101, MWS5101A

(PDIP, SBDIP)

TOP VIEW

DI1

R/W

CSI

O.D.

CS2

DO4

DI4

DO3

DI3

DO2

DO1 10

DI2 11

Ordering Information

MWS5101

PACKAGE

PDIP

Burn-In

SBDIP

Burn-In

TEMP. RANGE

C to +70

250ns

MWS5101EL2

350ns

MWS5101ELS

MWS5101A

250ns

MWS5101AEL2

350ns

MWS5101AEL3

PKG. NO.

E22.4

MWS5101AEL3X E22.4

MWS5101DL3X

MWS5101ADL3

D22.4A

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

Intersil Corporation 1999

File Number

1106.2

6-56

MWS5101AEL3X Related Products

	MWS5101AEL3X	MWS5101ELS	MWS5101EL2	MWS5101DL3X	MWS5101AEL3	MWS5101AEL2	MWS5101ADL3	MWS5101A	MWS5101
Description	256X4 STANDARD SRAM, 350ns, PDIP22, PLASTIC, DIP-22	256 X 4 STANDARD SRAM, 350 ns, PDIP22	256X4 STANDARD SRAM, 250ns, PDIP22, PLASTIC, DIP-22	256 X 4 STANDARD SRAM, 350 ns, CDIP22	256X4 STANDARD SRAM, 350ns, PDIP22, PLASTIC, DIP-22	256 X 4 STANDARD SRAM, 250 ns, PDIP22	256 X 4 STANDARD SRAM, 350 ns, CDIP22	256 X 4 STANDARD SRAM, 350 ns, PDIP22	256 X 4 STANDARD SRAM, 350 ns, PDIP22

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