Philips Semiconductors
Product specification
Latch/flip-flop
74ALS573B
74ALS574A
FEATURES
74ALS573B/74ALS574A
Octal transparent latch (3-State)
Octal D flip-flop (3-State)
It is an 8-bit edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of the D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The active-Low output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is Low, latched or
transparent data appears at the output.
When OE is High, the outputs are in high impedance “off” state,
which means they will neither drive nor load the bus.
TYPICAL
PROPAGATION
DELAY
5.0ns
6.0ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
12mA
15mA
•
74ALS573B is broadside pinout version of 74ALS373
•
74ALS574A is broadside pinout version of 74ALS374
•
Inputs and outputs on opposite side of package allow easy
interface to microprocessors
•
Useful as an input or output port for microprocessors
•
3-State outputs for bus interfacing
•
Common output enable
•
74ALS563A and 74ALS564A are inverting version of 74ALS573B
and 74ALS574A respectively
DESCRIPTION
The 74ALS573B is an octal transparent latch coupled to eight
3-State output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE) control gates.
The 74ALS573B is functionally identical to the 74ALS373 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocessors.
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is High. The latch remains transparent to the data
input while E is High, and stores the data that is present one setup
time before the High-to-Low enable transition.
The 74ALS574A is functionally identical to the 74ALS374 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocessors.
TYPE
74ALS573B
74ALS574A
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
20-pin plastic DIP
20-pin plastic SOL
20-pin plastic SSOP
Type II
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
74ALS573BN, 74ALS574AN
74ALS573BD, 74ALS574AD
74ALS573BDB,
74ALS574ADB
DRAWING
NUMBER
SOT146-1
SOT163-1
SOT339-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0 – D7
E (74ALS573B)
OE
CP (74ALS574A)
Q0 – Q7
Data inputs
Latch enable input
Output Enable input (active-Low)
Clock pulse input (active rising edge)
Data outputs
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/2.0
130/240
LOAD VALUE
HIGH/LOW
20µA/0.2mA
20µA/0.1mA
20µA/0.1mA
20µA/0.2mA
2.6mA/24mA
NOTE:
One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
1991 Feb 08
2
853–1307 01670
Philips Semiconductors
Product specification
Latch/flip-flop
74ALS573B/74ALS574A
LOGIC DIAGRAM – 74ALS573B
D0
2
D
E
E
11
D1
3
D
E
D2
4
D
E
D3
5
D
E
D4
6
D
E
D5
7
D
E
D6
8
D
E
D7
9
D
E
Q
Q
Q
Q
Q
Q
Q
Q
OE
1
19
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
V
CC
= Pin 20
GND = Pin 10
Q0
SC00109
FUNCTION TABLE – 74ALS573B
INPUTS
OE
L
L
L
L
L
H
H
H =
h =
L =
l =
NC=
X =
Z =
↓
=
E
H
H
↓
↓
L
L
H
Dn
L
H
l
h
X
X
Dn
OUTPUTS
REGISTER
L
H
L
H
NC
NC
Dn
INTERNAL
Q0 – Q7
L
H
L
H
NC
Z
Z
Disable outputs
Latch and read register
Hold
Enable and read register
OPERATING MODE
High-voltage level
High state must be present one setup time before the High-to-Low enable transition
Low-voltage level
Low state must be present one setup time before the High-to-Low enable transition
No change
Don’t care
High impedance “off” state
High-to-Low enable transition
LOGIC DIAGRAM – 74ALS574A
D0
2
D
CP Q
CP
11
D1
3
D
CP Q
D2
4
D
CP Q
D3
5
D
CP Q
D4
6
D
CP Q
D5
7
D
CP Q
D6
8
D
CP Q
D7
9
D
CP Q
OE
V
CC
= Pin 20
GND = Pin 10
1
19
Q0
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
SC00110
1991 Feb 08
4
Philips Semiconductors
Product specification
Latch/flip-flop
74ALS573B/74ALS574A
FUNCTION TABLE – 74ALS574A
INPUTS
OE
L
L
L
H
H
H =
h =
L =
l =
NC=
X =
Z =
↑
=
↑
=
CP
↑
↑
↑
↑
↑
Dn
l
h
X
X
Dn
OUTPUTS
REGISTER
L
H
NC
NC
Dn
INTERNAL
Q0 – Q7
L
H
NC
Z
Z
Disable outputs
Latch and read register
Hold
OPERATING MODE
High-voltage level
High state must be present one setup time before the Low-to-High clock transition
Low-voltage level
Low state must be present one setup time before the Low-to-High clock transition
No change
Don’t care
High impedance “off” state
Low-to-High clock transition
Not Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
48
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
amb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature range
0
PARAMETER
MIN
4.5
2.0
0.8
–18
–2.6
24
+70
NOM
5.0
MAX
5.5
V
V
V
mA
mA
mA
°C
UNIT
1991 Feb 08
5
DIY/Open Source Hardware
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