74LVC1G80GV,125 datasheet, PDF

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74LVC1G80GV,125: Descriptionflip flops single D type triger; Categorylogic logic; File Size368KB，21 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74LVC1G80GV,125 Overview

flip flops single D type triger

74LVC1G80GV,125 Parametric

Parameter Name	Attribute value
Brand Name	NXP Semiconductor
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	TSOP
package instruction	TSSOP, TSOP5/6,.11,37
Contacts	5
Manufacturer packaging code	SOT753
Reach Compliance Code	compliant
series	LVC/LCX/Z
JESD-30 code	R-PDSO-G5
JESD-609 code	e3
length	2.9 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	D FLIP-FLOP
MaximumI(ol)	0.024 A
Humidity sensitivity level	1
Number of digits	1
Number of functions	1
Number of terminals	5
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output polarity	INVERTED
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSOP5/6,.11,37
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
propagation delay (tpd)	13 ns
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	1.65 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.95 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Trigger type	POSITIVE EDGE
width	1.5 mm
minfmax	200 MHz

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74LVC1G80

Single D-type flip-flop; positive-edge trigger

Rev. 12 — 2 July 2012

Product data sheet

1. General description

The 74LVC1G80 provides a single positive-edge triggered D-type flip-flop.

Information on the data input is transferred to the Q output on the LOW-to-HIGH transition

of the clock pulse. The input pin D must be stable one set-up time prior to the

LOW-to-HIGH clock transition for predictable operation.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this

device in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using I

OFF

. The I

OFF

circuitry disables the output, preventing the damaging backflow current through the device

when it is powered down.

2. Features and benefits



Wide supply voltage range from 1.65 V to 5.5 V



High noise immunity



Complies with JEDEC standard:



JESD8-7 (1.65 V to 1.95 V)



JESD8-5 (2.3 V to 2.7 V)



JESD8B/JESD36 (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V



24

mA output drive (V

= 3.0 V)



CMOS low power consumption



Latch-up performance exceeds 250 mA



Direct interface with TTL levels



Inputs accept voltages up to 5 V



Multiple package options



Specified from

40 C

to +85

C

and

40 C

to +125

C.

74LVC1G80GV,125 Related Products

	74LVC1G80GV,125	74LVC1G80GM,132	74LVC1G80GF,132	74LVC1G80GS,132
Description	flip flops single D type triger	flip flops single D-type	flip flops flip flop D-type pos-edge 1-elm 6-pin	translation - voltage levels 13ns 5.5V 250mw
Brand Name	NXP Semiconductor	NXP Semiconduc	NXP Semiconduc	NXP Semiconductor
Is it Rohs certified?	conform to	conform to	conform to	conform to
Maker	NXP	NXP	NXP	NXP
package instruction	TSSOP, TSOP5/6,.11,37	VSON, SOLCC6,.04,20	VSON, SOLCC6,.04,14	1 X 1 MM, 0.35 MM HEIGHT, 0.35 MM PITCH, SOT-1202, SON-6
Manufacturer packaging code	SOT753	SOT886	SOT891	SOT1202
Reach Compliance Code	compliant	compli	compli	compliant
Parts packaging code	TSOP	SON	SON	-
Contacts	5	6	6	-
series	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	-
JESD-30 code	R-PDSO-G5	R-PDSO-N6	S-PDSO-N6	-
JESD-609 code	e3	e3	e3	-
length	2.9 mm	1.45 mm	1 mm	-
Load capacitance (CL)	50 pF	50 pF	50 pF	-
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	-
MaximumI(ol)	0.024 A	0.024 A	0.024 A	-
Humidity sensitivity level	1	1	1	-
Number of digits	1	1	1	-
Number of functions	1	1	1	-
Number of terminals	5	6	6	-
Maximum operating temperature	125 °C	125 °C	125 °C	-
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-
Output polarity	INVERTED	INVERTED	INVERTED	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	TSSOP	VSON	VSON	-
Encapsulate equivalent code	TSOP5/6,.11,37	SOLCC6,.04,20	SOLCC6,.04,14	-
Package shape	RECTANGULAR	RECTANGULAR	SQUARE	-
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, VERY THIN PROFILE	-
method of packing	TAPE AND REEL	TAPE AND REEL	TAPE AND REEL	-
Peak Reflow Temperature (Celsius)	260	260	260	-
power supply	3.3 V	3.3 V	3.3 V	-
propagation delay (tpd)	13 ns	13 ns	13 ns	-
Certification status	Not Qualified	Not Qualified	Not Qualified	-
Maximum seat height	1.1 mm	0.5 mm	0.5 mm	-
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	-
Minimum supply voltage (Vsup)	1.65 V	1.65 V	1.65 V	-
Nominal supply voltage (Vsup)	3.3 V	1.8 V	1.8 V	-
surface mount	YES	YES	YES	-
technology	CMOS	CMOS	CMOS	-
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	-
Terminal surface	Tin (Sn)	Tin (Sn)	Tin (Sn)	-
Terminal form	GULL WING	NO LEAD	NO LEAD	-
Terminal pitch	0.95 mm	0.5 mm	0.35 mm	-
Terminal location	DUAL	DUAL	DUAL	-
Maximum time at peak reflow temperature	30	40	40	-
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	-
width	1.5 mm	1 mm	1 mm	-
minfmax	200 MHz	200 MHz	200 MHz	-

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